linux-kernel - [PATCH v2 1/4] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for XilSem

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250722160315.2979294-2-rama.devi.veggalam@amd.com>
Date: Tue, 22 Jul 2025 21:33:12 +0530
From: Rama devi Veggalam <rama.devi.veggalam@....com>
To: <bp@...en8.de>, <tony.luck@...el.com>, <michal.simek@....com>,
	<robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>
CC: <linux-kernel@...r.kernel.org>, <linux-edac@...r.kernel.org>,
	<devicetree@...r.kernel.org>, <james.morse@....com>, <mchehab@...nel.org>,
	<rric@...nel.org>, <git@....com>, Rama devi Veggalam
	<rama.devi.veggalam@....com>
Subject: [PATCH v2 1/4] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for XilSem

Add device tree bindings for Xilinx Versal EDAC for
XilSem controller

Signed-off-by: Rama devi Veggalam <rama.devi.veggalam@....com>
---
Changes in v2:
- Changed "xlnx,versal-xilsem-edac" to constant
- Removed "compatible: in required section
- Removed "|" in description
- Removed "items" in compatible
- Fixed indentation in examples
- Updated title and description
---
 .../edac/xlnx,versal-xilsem-edac.yaml         | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml

diff --git a/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml b/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml
new file mode 100644
index 000000000000..23c1d0557a66
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/xlnx,versal-xilsem-edac.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/xlnx,versal-xilsem-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal Soft Error Mitigation (XilSEM) EDAC
+
+maintainers:
+  - Rama Devi Veggalam <rama.devi.veggalam@....com>
+
+description:
+  Xilinx Versal Soft Error Mitigation (XilSEM) is part of the
+  Platform Loader and Manager (PLM) which is loaded into and runs on the
+  Platform Management Controller (PMC). XilSEM is responsible for reporting
+  and optionally correcting soft errors in Configuration Memory of Versal.
+  The memory is scanned by a hardware controller in the Versal Programmable
+  Logic (PL). During the scan, if the controller detects any error, be it
+  correctable or uncorrectable, it reports the error to PLM. The XilSEM on PLM
+  performs the error validation and notifies the errors to user application.
+  This XilSEM EDAC node is responsible for handling error events received from
+  XilSEM on PLM and also provides an interface to control scan operations and
+  fetching the scan status & configuration information.
+
+properties:
+  compatible:
+    const: xlnx,versal-xilsem-edac
+
+  reg:
+    maxItems: 1
+
+required:
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    edac@...14050 {
+        compatible = "xlnx,versal-xilsem-edac";
+        reg = <0xf2014050 0xc4>;
+    };
-- 
2.23.0