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Message-ID: <02d1fa2a-0faf-44db-a683-53c5a51e09f1@oss.qualcomm.com>
Date: Wed, 23 Jul 2025 03:11:03 +0530
From: Akhil P Oommen <akhilpo@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 16/17] drm/msm/a6xx: Enable IFPC on Adreno X1-85
On 7/22/2025 8:25 PM, Konrad Dybcio wrote:
> On 7/20/25 2:16 PM, Akhil P Oommen wrote:
>> Add the IFPC restore register list and enable IFPC support on Adreno
>> X1-85 gpu.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 67 ++++++++++++++++++++++++++++++-
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++--
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
>> 3 files changed, 78 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 70f7ad806c34076352d84f32d62c2833422b6e5e..07fcabed472c3b9ca47faf1a8b3f7cf580801981 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1343,6 +1343,69 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = {
>>
>> DECLARE_ADRENO_REGLIST_LIST(a7xx_pwrup_reglist);
>>
>> +/* Applicable for X185, A750 */
>> +static const u32 a750_ifpc_reglist_regs[] = {
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
>> + REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
>> + REG_A6XX_TPL1_NC_MODE_CNTL,
>> + REG_A6XX_SP_NC_MODE_CNTL,
>> + REG_A6XX_CP_DBG_ECO_CNTL,
>> + REG_A6XX_CP_PROTECT_CNTL,
>> + REG_A6XX_CP_PROTECT(0),
>> + REG_A6XX_CP_PROTECT(1),
>
> Is it fair to assume that we'd like to saverestore all CP_PROT
> registers on all SKUs, always? We can save some space in .rodata
> this way..
Yeah. Makes sense, but lets do that when we duplicate it in future.
-Akhil
>
> Konrad
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