lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250722055039.135140-1-raviteja.laggyshetty@oss.qualcomm.com>
Date: Tue, 22 Jul 2025 05:50:38 +0000
From: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
To: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Odelu Kukatla <quic_okukatla@...cinc.com>,
        Imran Shaik <quic_imrashai@...cinc.com>,
        Mike Titpon <mike.tipton@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
Subject: [PATCH V3 0/1] Add EPSS L3 provider support on QCS8300 SoC

 Add Epoch subsystem (EPSS) L3 scaling support on QCS8300 SoC.

Changes since V2:
 - Dropped the dt-binding patch from series, as it has been picked into
   linux-next
   https://lore.kernel.org/all/20250711102540.143-2-raviteja.laggyshetty@oss.qualcomm.com/
 - Squashed EPSS L3 provider node changes and CPU OPP table changes into 
   single patch [Konrad].
 - Link to v2: https://lore.kernel.org/all/20250711102540.143-1-raviteja.laggyshetty@oss.qualcomm.com/

Changes since v1:
 - Removed SoC specific compatible "qcom,qcs8300-epss-l3"
   from driver and used SA8775P SoC compatible as fallback in devicetree.
 - As the EPSS hardware in QCS8300 and SA8775P SoCs are same, a 
   family-specific compatible string for the SA8775P has been added to the
   bindings. This avoids the need to explicitly listing each SoC in the
   match table and the family-specific fallback compatible can be used 
   for SoCs sharing the same hardware.
 - As suggested by konrad, added EPSS path handles for CPU nodes.
 - Link to v1: https://lore.kernel.org/all/20250617090651.55-1-raviteja.laggyshetty@oss.qualcomm.com/

Raviteja Laggyshetty (1):
  arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and
    CPUCP OPP tables to scale DDR/L3

 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 301 ++++++++++++++++++++++++++
 1 file changed, 301 insertions(+)

-- 
2.43.0


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ