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Message-Id: <20250722-add-displayport-support-for-qcs615-platform-v2-13-42b4037171f8@oss.qualcomm.com>
Date: Tue, 22 Jul 2025 15:22:14 +0800
From: Xiangxu Yin <xiangxu.yin@....qualcomm.com>
To: Rob Clark <robin.clark@....qualcomm.com>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
dmitry.baryshkov@....qualcomm.com, konrad.dybcio@....qualcomm.com,
fange.zhang@....qualcomm.com, quic_lliu6@...cinc.com,
quic_yongmou@...cinc.com, Xiangxu Yin <xiangxu.yin@....qualcomm.com>
Subject: [PATCH v2 13/13] drm/msm/dp: Add support for lane mapping
configuration
Since max_dp_lanes and max_dp_link_rate are link-specific parameters,
move their parsing from dp_panel to dp_link for better separation
of concerns.
Add lane mapping configuration for the DisplayPort (DP) controller on
the QCS615 platform.
QCS615 platform requires non-default logical-to-physical lane mapping
due to its unique hardware routing. Unlike the standard mapping sequence
<0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit
configuration via the data-lanes property in the device tree. This
ensures correct signal routing between the DP controller and PHY.
The DP PHY supports polarity inversion (PN swap) but does not support
lane swapping. Therefore, lane mapping should be handled in the DP
controller domain using REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING.
Signed-off-by: Xiangxu Yin <xiangxu.yin@....qualcomm.com>
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 ++---
drivers/gpu/drm/msm/dp/dp_link.c | 71 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/dp/dp_link.h | 5 +++
drivers/gpu/drm/msm/dp/dp_panel.c | 78 +++++----------------------------------
drivers/gpu/drm/msm/dp/dp_panel.h | 3 --
5 files changed, 90 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index c42fd2c17a328f6deae211c9cd57cc7416a9365a..cbcc7c2f0ffc4696749b6c43818d20853ddec069 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -423,13 +423,13 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl)
static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl)
{
- u32 ln_0 = 0, ln_1 = 1, ln_2 = 2, ln_3 = 3; /* One-to-One mapping */
+ u32 *lane_map = ctrl->link->lane_map;
u32 ln_mapping;
- ln_mapping = ln_0 << LANE0_MAPPING_SHIFT;
- ln_mapping |= ln_1 << LANE1_MAPPING_SHIFT;
- ln_mapping |= ln_2 << LANE2_MAPPING_SHIFT;
- ln_mapping |= ln_3 << LANE3_MAPPING_SHIFT;
+ ln_mapping = lane_map[0] << LANE0_MAPPING_SHIFT;
+ ln_mapping |= lane_map[1] << LANE1_MAPPING_SHIFT;
+ ln_mapping |= lane_map[2] << LANE2_MAPPING_SHIFT;
+ ln_mapping |= lane_map[3] << LANE3_MAPPING_SHIFT;
msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING,
ln_mapping);
diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
index 66e1bbd80db3a28f5f16d083486752007ceaf3f7..7c7a4aa584eb42a0ca7c6ec45de585cde8639cb4 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.c
+++ b/drivers/gpu/drm/msm/dp/dp_link.c
@@ -6,12 +6,14 @@
#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
#include <drm/drm_device.h>
+#include <drm/drm_of.h>
#include <drm/drm_print.h>
#include "dp_reg.h"
#include "dp_link.h"
#include "dp_panel.h"
+#define DP_LINK_RATE_HBR2 540000 /* kbytes */
#define DP_TEST_REQUEST_MASK 0x7F
enum audio_sample_rate {
@@ -37,6 +39,7 @@ struct msm_dp_link_request {
struct msm_dp_link_private {
u32 prev_sink_count;
+ struct device *dev;
struct drm_device *drm_dev;
struct drm_dp_aux *aux;
struct msm_dp_link msm_dp_link;
@@ -1210,10 +1213,73 @@ u32 msm_dp_link_get_test_bits_depth(struct msm_dp_link *msm_dp_link, u32 bpp)
return tbd;
}
+static u32 msm_dp_link_link_frequencies(struct device_node *of_node)
+{
+ struct device_node *endpoint;
+ u64 frequency = 0;
+ int cnt;
+
+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
+ if (!endpoint)
+ return 0;
+
+ cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
+
+ if (cnt > 0)
+ of_property_read_u64_index(endpoint, "link-frequencies",
+ cnt - 1, &frequency);
+ of_node_put(endpoint);
+
+ do_div(frequency,
+ 10 * /* from symbol rate to link rate */
+ 1000); /* kbytes */
+
+ return frequency;
+}
+
+static int msm_dp_link_parse_dt(struct msm_dp_link *msm_dp_link)
+{
+ struct msm_dp_link_private *link;
+ struct device_node *of_node;
+ int cnt;
+ u32 lane_map[DP_MAX_NUM_DP_LANES] = {0};
+
+ link = container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_link);
+ of_node = link->dev->of_node;
+
+ /*
+ * data-lanes is the property of msm_dp_out endpoint
+ */
+ cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
+ if (cnt < 0) {
+ /* legacy code, data-lanes is the property of mdss_dp node */
+ cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
+ }
+
+ if (cnt > 0) {
+ struct device_node *endpoint;
+
+ msm_dp_link->max_dp_lanes = cnt;
+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, -1);
+ of_property_read_u32_array(endpoint, "data-lanes", lane_map, cnt);
+ } else {
+ msm_dp_link->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
+ }
+
+ memcpy(msm_dp_link->lane_map, lane_map, msm_dp_link->max_dp_lanes * sizeof(u32));
+
+ msm_dp_link->max_dp_link_rate = msm_dp_link_link_frequencies(of_node);
+ if (!msm_dp_link->max_dp_link_rate)
+ msm_dp_link->max_dp_link_rate = DP_LINK_RATE_HBR2;
+
+ return 0;
+}
+
struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux *aux)
{
struct msm_dp_link_private *link;
struct msm_dp_link *msm_dp_link;
+ int ret;
if (!dev || !aux) {
DRM_ERROR("invalid input\n");
@@ -1225,9 +1291,14 @@ struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux *aux)
return ERR_PTR(-ENOMEM);
link->aux = aux;
+ link->dev = dev;
mutex_init(&link->psm_mutex);
msm_dp_link = &link->msm_dp_link;
+ ret = msm_dp_link_parse_dt(msm_dp_link);
+ if (ret)
+ return ERR_PTR(ret);
+
return msm_dp_link;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_link.h
index ba47c6d19fbfacfc58031263e4a2f5a6d9c2c229..b1eb2de6d2a7693f17aa2f256657110af839533d 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.h
+++ b/drivers/gpu/drm/msm/dp/dp_link.h
@@ -12,6 +12,7 @@
#define DS_PORT_STATUS_CHANGED 0x200
#define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF
#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
+#define DP_MAX_NUM_DP_LANES 4
struct msm_dp_link_info {
unsigned char revision;
@@ -72,6 +73,10 @@ struct msm_dp_link {
struct msm_dp_link_test_audio test_audio;
struct msm_dp_link_phy_params phy_params;
struct msm_dp_link_info link_params;
+
+ u32 lane_map[DP_MAX_NUM_DP_LANES];
+ u32 max_dp_lanes;
+ u32 max_dp_link_rate;
};
/**
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 15b7f6c7146e1176a80b5c9d25896b1c8ede3aed..ad5d55bf009dbe60e61ca4f4c108116333129203 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -16,9 +16,6 @@
#define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4)
-#define DP_MAX_NUM_DP_LANES 4
-#define DP_LINK_RATE_HBR2 540000 /* kbytes */
-
struct msm_dp_panel_private {
struct device *dev;
struct drm_device *drm_dev;
@@ -91,6 +88,7 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
int rc, max_lttpr_lanes, max_lttpr_rate;
struct msm_dp_panel_private *panel;
struct msm_dp_link_info *link_info;
+ struct msm_dp_link *link;
u8 *dpcd, major, minor;
panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
@@ -105,16 +103,20 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
major = (link_info->revision >> 4) & 0x0f;
minor = link_info->revision & 0x0f;
+ link = panel->link;
+ drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
+ link->max_dp_lanes, link->max_dp_link_rate);
+
link_info->rate = drm_dp_max_link_rate(dpcd);
link_info->num_lanes = drm_dp_max_lane_count(dpcd);
/* Limit data lanes from data-lanes of endpoint property of dtsi */
- if (link_info->num_lanes > msm_dp_panel->max_dp_lanes)
- link_info->num_lanes = msm_dp_panel->max_dp_lanes;
+ if (link_info->num_lanes > link->max_dp_lanes)
+ link_info->num_lanes = link->max_dp_lanes;
/* Limit link rate from link-frequencies of endpoint property of dtsi */
- if (link_info->rate > msm_dp_panel->max_dp_link_rate)
- link_info->rate = msm_dp_panel->max_dp_link_rate;
+ if (link_info->rate > link->max_dp_link_rate)
+ link_info->rate = link->max_dp_link_rate;
/* Limit data lanes from LTTPR capabilities, if any */
max_lttpr_lanes = drm_dp_lttpr_max_lane_count(panel->link->lttpr_common_caps);
@@ -173,9 +175,6 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel,
panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
- drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n",
- msm_dp_panel->max_dp_lanes, msm_dp_panel->max_dp_link_rate);
-
rc = msm_dp_panel_read_dpcd(msm_dp_panel);
if (rc) {
DRM_ERROR("read dpcd failed %d\n", rc);
@@ -648,60 +647,6 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel)
return 0;
}
-static u32 msm_dp_panel_link_frequencies(struct device_node *of_node)
-{
- struct device_node *endpoint;
- u64 frequency = 0;
- int cnt;
-
- endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
- if (!endpoint)
- return 0;
-
- cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
-
- if (cnt > 0)
- of_property_read_u64_index(endpoint, "link-frequencies",
- cnt - 1, &frequency);
- of_node_put(endpoint);
-
- do_div(frequency,
- 10 * /* from symbol rate to link rate */
- 1000); /* kbytes */
-
- return frequency;
-}
-
-static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel)
-{
- struct msm_dp_panel_private *panel;
- struct device_node *of_node;
- int cnt;
-
- panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel);
- of_node = panel->dev->of_node;
-
- /*
- * data-lanes is the property of msm_dp_out endpoint
- */
- cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
- if (cnt < 0) {
- /* legacy code, data-lanes is the property of mdss_dp node */
- cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
- }
-
- if (cnt > 0)
- msm_dp_panel->max_dp_lanes = cnt;
- else
- msm_dp_panel->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
-
- msm_dp_panel->max_dp_link_rate = msm_dp_panel_link_frequencies(of_node);
- if (!msm_dp_panel->max_dp_link_rate)
- msm_dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2;
-
- return 0;
-}
-
struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux,
struct msm_dp_link *link,
void __iomem *link_base,
@@ -709,7 +654,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux
{
struct msm_dp_panel_private *panel;
struct msm_dp_panel *msm_dp_panel;
- int ret;
if (!dev || !aux || !link) {
DRM_ERROR("invalid input\n");
@@ -729,10 +673,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux
msm_dp_panel = &panel->msm_dp_panel;
msm_dp_panel->max_bw_code = DP_LINK_BW_8_1;
- ret = msm_dp_panel_parse_dt(msm_dp_panel);
- if (ret)
- return ERR_PTR(ret);
-
return msm_dp_panel;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
index d2cf401506dcbaf553192d5e18c87207337664ab..921a296852d4df65f817665d3e1344f2f7c9ece7 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -41,9 +41,6 @@ struct msm_dp_panel {
bool vsc_sdp_supported;
u32 hw_revision;
- u32 max_dp_lanes;
- u32 max_dp_link_rate;
-
u32 max_bw_code;
};
--
2.34.1
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