linux-kernel - Re: [PATCH] drm/ttm: add pgprot handling for RISC-V

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Message-ID: <CAAT7Ki9DUJhZgqW7e4ggcgHM9K21ExAEMbK=WjOiVged0+=fCA@mail.gmail.com>
Date: Tue, 22 Jul 2025 19:25:25 +0800
From: Han Gao <rabenda.cn@...il.com>
To: Icenowy Zheng <uwu@...nowy.me>
Cc: Christian Koenig <christian.koenig@....com>, Huang Rui <ray.huang@....com>, 
	Matthew Auld <matthew.auld@...el.com>, Matthew Brost <matthew.brost@...el.com>, 
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, 
	Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, dri-devel@...ts.freedesktop.org, 
	linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org, 
	Vivian Wang <wangruikang@...as.ac.cn>, Inochi Amaoto <inochiama@...il.com>, 
	Yao Zi <ziyao@...root.org>
Subject: Re: [PATCH] drm/ttm: add pgprot handling for RISC-V

On Tue, Jul 22, 2025 at 7:21 PM Icenowy Zheng <uwu@...nowy.me> wrote:
>
> The RISC-V Svpbmt privileged extension provides support for overriding
> page memory coherency attributes, and, along with vendor extensions like
> Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
>
> Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
> and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
> access attributes.
>
> Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
> ---
>  drivers/gpu/drm/ttm/ttm_module.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
> index b3fffe7b5062..aa137ead5cc5 100644
> --- a/drivers/gpu/drm/ttm/ttm_module.c
> +++ b/drivers/gpu/drm/ttm/ttm_module.c
> @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp)
>  #endif /* CONFIG_UML */
>  #endif /* __i386__ || __x86_64__ */
>  #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \
> -       defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)
> +       defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \
> +       defined(__riscv)
>         if (caching == ttm_write_combined)
>                 tmp = pgprot_writecombine(tmp);
>         else
> --
> 2.50.1
>

Tested-by: Han Gao <rabenda.cn@...il.com>

Thanks.