linux-kernel - Re: [PATCH v5 3/4] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy

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Message-ID: <aH-Ce0obEcm1S2N9@hovoldconsulting.com>
Date: Tue, 22 Jul 2025 14:22:19 +0200
From: Johan Hovold <johan@...nel.org>
To: Ziyue Zhang <ziyue.zhang@....qualcomm.com>
Cc: Konrad Dybcio <konrad.dybcio@....qualcomm.com>, andersson@...nel.org,
	konradybcio@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
	conor+dt@...nel.org, jingoohan1@...il.com, mani@...nel.org,
	lpieralisi@...nel.org, kwilczynski@...nel.org, bhelgaas@...gle.com,
	johan+linaro@...nel.org, vkoul@...nel.org, kishon@...nel.org,
	neil.armstrong@...aro.org, abel.vesa@...aro.org, kw@...ux.com,
	linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
	linux-phy@...ts.infradead.org, qiang.yu@....qualcomm.com,
	quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: [PATCH v5 3/4] arm64: dts: qcom: sa8775p: remove aux clock from
 pcie phy

On Tue, Jul 22, 2025 at 01:13:34PM +0800, Ziyue Zhang wrote:
> On 7/18/2025 6:53 PM, Konrad Dybcio wrote:
> > On 7/18/25 12:02 PM, Johan Hovold wrote:
> >> On Fri, Jul 18, 2025 at 04:17:17PM +0800, Ziyue Zhang wrote:
> >>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in
> >>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and
> >>> replace it with gcc_phy_aux_clk.
> >> Expanding on why this is a correct change would be good since this does
> >> not yet seem to have been fully resolved:
> >>
> >> 	https://lore.kernel.org/lkml/98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com/

> > I dug out some deep memories and recalled that _PHY_AUX_CLK was
> > necessary on x1e for the Gen4 PHY to initialize properly. This
> > can be easily reproduced:

> > @@ -3312,7 +3312,7 @@ pcie3_phy: phy@...0000 {
> >                          compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
> >                          reg = <0 0x01be0000 0 0x10000>;
> >   
> > -                       clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
> > +                       clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
> >                                   <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
> >                                   <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
> >                                   <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
> >
> > ==>
> > [    6.967231] qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out
> > [    6.974462] phy phy-1be0000.phy.0: phy poweron failed --> -110
> >
> > And the (non-PHY_)AUX_CLK is necessary for at least one of them, as
> > removing it causes a crash on boot

Thanks for checking. I too had noticed that the pcie4 and pcie5 was
using the non-phy aux clocks, and those are indeed gen3.

> I tried remove PHY_AUX_CLK in sa8775p platform like this, and
> it will cause a crash on boot. And I checked the clock documentation
> for sa8775p and found that the PHY_AUX_CLK  is also required.

Thanks, would still be good to say something in the commit message about
the difference between the PHY_AUX_CLK and AUX_CLK clocks and why
(only?) the gen4 PHYs need it (we seem to have other Qualcomm non-gen4
PHYs using the PHY_AUX clock too).

That is, please clarify which PHYs need the PHY_AUX_CLK and why they
don't also need the AUX_CLK like some PHYs do.

Johan