linux-kernel - Re: [PATCH v3 3/3] arm64: cacheinfo: Provide helper to compress MPIDR value into u32

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Message-ID: <aH-Z0SNzNVz0cToB@willie-the-truck>
Date: Tue, 22 Jul 2025 15:01:53 +0100
From: Will Deacon <will@...nel.org>
To: James Morse <james.morse@....com>
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	"Rafael J . Wysocki" <rafael@...nel.org>, sudeep.holla@....com,
	Rob Herring <robh@...nel.org>, Ben Horgan <ben.horgan@....com>,
	Jonathan Cameron <jonathan.cameron@...wei.com>,
	Catalin Marinas <catalin.marinas@....com>,
	Gavin Shan <gshan@...hat.com>
Subject: Re: [PATCH v3 3/3] arm64: cacheinfo: Provide helper to compress
 MPIDR value into u32

On Fri, Jul 11, 2025 at 06:27:43PM +0000, James Morse wrote:
> Filesystems like resctrl use the cache-id exposed via sysfs to identify
> groups of CPUs. The value is also used for PCIe cache steering tags. On
> DT platforms cache-id is not something that is described in the
> device-tree, but instead generated from the smallest MPIDR of the CPUs
> associated with that cache. The cache-id exposed to user-space has
> historically been 32 bits.
> 
> MPIDR values may be larger than 32 bits.
> 
> MPIDR only has 32 bits worth of affinity data, but the aff3 field lives
> above 32bits. The corresponding lower bits are masked out by
> MPIDR_HWID_BITMASK and contain an SMT flag and Uni-Processor flag.
> 
> Swizzzle the aff3 field into the bottom 32 bits and using that.
> 
> In case more affinity fields are added in the future, the upper RES0
> area should be checked. Returning a value greater than 32 bits from
> this helper will cause the caller to give up on allocating cache-ids.
> 
> Signed-off-by: James Morse <james.morse@....com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@...wei.com>
> Reviewed-by: Gavin Shan <gshan@...hat.com>
> ---
> Changes since v1:
>  * Removal of unrelated changes.
>  * Added a comment about how the RES0 bit safety net works.
> ---
>  arch/arm64/include/asm/cache.h | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> index 99cd6546e72e..09963004ceea 100644
> --- a/arch/arm64/include/asm/cache.h
> +++ b/arch/arm64/include/asm/cache.h
> @@ -87,6 +87,23 @@ int cache_line_size(void);
>  
>  #define dma_get_cache_alignment	cache_line_size
>  
> +/* Compress a u64 MPIDR value into 32 bits. */
> +static inline u64 arch_compact_of_hwid(u64 id)
> +{
> +	u64 aff3 = MPIDR_AFFINITY_LEVEL(id, 3);
> +
> +	/*
> +	 * These bits are expected to be RES0. If not, return a value with
> +	 * the upper 32 bits set to force the caller to give up on 32 bit
> +	 * cache ids.
> +	 */
> +	if (FIELD_GET(GENMASK_ULL(63, 40), id))
> +		return id;

Why is it safe to ignore the other RES bits (i.e. 31, 29:25)? If the
architects decide to pack some additional affinity information in there,
we're in trouble, no?

Will