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Message-ID: <20250722-ddrperfm-upstream-v3-0-7b7a4f3dc8a0@foss.st.com>
Date: Tue, 22 Jul 2025 16:03:17 +0200
From: Clément Le Goffic <clement.legoffic@...s.st.com>
To: Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
Rob
Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor
Dooley <conor+dt@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Philipp Zabel
<p.zabel@...gutronix.de>,
Jonathan Corbet <corbet@....net>,
Gatien Chevallier
<gatien.chevallier@...s.st.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Gabriel Fernandez
<gabriel.fernandez@...s.st.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Le
Goffic <legoffic.clement@...il.com>,
Julius Werner <jwerner@...omium.org>
CC: <linux-arm-kernel@...ts.infradead.org>, <linux-perf-users@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-kernel@...r.kernel.org>, <linux-doc@...r.kernel.org>,
<linux-clk@...r.kernel.org>,
Clément Le Goffic <clement.legoffic@...s.st.com>
Subject: [PATCH v3 00/19] Introduce STM32 DDR PMU for STM32MP platforms
This patch series introduces the DDR Performance Monitor (DDRPERFM) support for
STM32MP platforms.
The series improves the STM32MP25 RCC driver to make it usable
as an access controller, needed for driver probe.
The series introduces support of DDR channel through dt-binding and
devicetree entries.
It also includes the addition of DDRPERFM device tree bindings,
the DDRPERFM driver, the documentation and updates to the device tree files
for STM32MP13, STM32MP15, STM32MP25 SoCs and stm32mp257f-dk and
stm32mp257f-ev1 boards.
The series also updates the MAINTAINERS file to include myself as the
maintainer for the STM32 DDR PMU driver.
Signed-off-by: Clément Le Goffic <clement.legoffic@...s.st.com>
---
Changes in v3:
- dt-bindings:
- perf:
- fix compatible conditions and dtbs_check/dt_binding_check errors
- memory:
- Remove ddr-channel binding added in v2
- Generalise lpddr-props binding into memory-props binding
- Add ddr4 binding
- Generalise lpddr-channel binding into memory-channel-binding
- devicetree:
- update stm32mp257f-ev1 board devicetree as per new ddr4-channel
binding
- driver:
- Remove unneeded pmu and event pointer tests in
`stm32_ddr_pmu_get_counter()` as it would break before if they are
NULL
- Rename macro to be more driver specific
- Fix few trailing commas in array and enum last entries
- Stick to the use of `pmu->dev` in the probe instead of
`&pdev->dev`
- s/devm_clk_get_optional_prepared/devm_clk_get_optional_enabled/ to
fix unwinding issue and remove the `clk_enable()` of the probe.
- Move the `perf_pmu_register()` at the end of the probe
- Add lacking spaces in regspec structs
- Use DEFINE_SIMPLE_DEV_PM_OPS instead of SET_SYSTEM_SLEEP_PM_OPS
- Link to v2: https://lore.kernel.org/r/20250711-ddrperfm-upstream-v2-0-cdece720348f@foss.st.com
Changes in v2:
- MAINTAINERS:
Due to reorganisation, my contract with ST ends at the end of this month
and I will no longer have access to this mailbox.
Therefore, I will be available for any mission related to embedded and
kernel linux.
Change email address in MAINTAINERS file for STM32 DDR PMU driver.
- devicetrees:
-stm32mp257f-dk: add LPDDR4 channel
-stm32mp257f-ev1: add DDR4 channel
- dt-bindings:
- perf:
- Change Maintainer email address
- Drop obvious descriptions (clocks and reset property)
- Drop redundant "bindings" in commit message
- Drop unneedded "stm32mp151-ddr-pmu" compatible
- s/st,dram-type/memory-channel/, memory-channel property is not in
dtschema library so it will produce an error in the v2.
- rcc:
- Add required "access-controller-cells" property in example
- ddr-channel:
- Add bindings as per jedec,lpddrX-channel bindings
- driver:
- Substitute the parsing of the 'st,dram-type' vendor devicetree
property value with the parsing of the [lp]ddr channel compatible
- Remove unneeded "stm32mp151-ddr-pmu" compatible
- Use dev_err_probe when possible
- Assert and deassert reset line unconditionnaly
- Use `devm_reset_control_get_optional_exclusive` instead of
`of_property_present` then `devm_reset_control_get`
- Use `devm_clk_get_optional_prepared` instead of `of_property_present`
then `devm_clk_get_prepared`
- Disable and unprepare the clock at end of probe
- Add io.h include as per LKP test report
- Removed `of_match_ptr` reference in `platform_driver` struct
- Add `pm_sleep_ptr` macro for `platform_driver` struct's `pm` field
- Link to v1: https://lore.kernel.org/r/20250623-ddrperfm-upstream-v1-0-7dffff168090@foss.st.com
---
Clément Le Goffic (19):
bus: firewall: move stm32_firewall header file in include folder
dt-bindings: stm32: stm32mp25: add `access-controller-cell` property
clk: stm32mp25: add firewall grant_access ops
arm64: dts: st: set rcc as an access-controller
dt-bindings: memory: factorise LPDDR props into memory props
dt-bindings: memory: introduce DDR4
dt-bindings: memory: factorise LPDDR channel binding into memory channel
dt-binding: memory: add DDR4 channel compatible
arm64: dts: st: add LPDDR channel to stm32mp257f-dk board
arm64: dts: st: add DDR channel to stm32mp257f-ev1 board
dt-bindings: perf: stm32: introduce DDRPERFM dt-bindings
perf: stm32: introduce DDRPERFM driver
Documentation: perf: stm32: add ddrperfm support
MAINTAINERS: add myself as STM32 DDR PMU maintainer
ARM: dts: stm32: add ddrperfm on stm32mp131
ARM: dts: stm32: add ddrperfm on stm32mp151
arm64: dts: st: add ddrperfm on stm32mp251
arm64: dts: st: support ddrperfm on stm32mp257f-dk
arm64: dts: st: support ddrperfm on stm32mp257f-ev1
Documentation/admin-guide/perf/index.rst | 1 +
Documentation/admin-guide/perf/stm32-ddr-pmu.rst | 86 ++
.../bindings/clock/st,stm32mp25-rcc.yaml | 7 +
.../memory-controllers/ddr/jedec,ddr4.yaml | 34 +
.../memory-controllers/ddr/jedec,lpddr2.yaml | 2 +-
.../memory-controllers/ddr/jedec,lpddr3.yaml | 2 +-
.../memory-controllers/ddr/jedec,lpddr4.yaml | 2 +-
.../memory-controllers/ddr/jedec,lpddr5.yaml | 2 +-
...pddr-channel.yaml => jedec,memory-channel.yaml} | 36 +-
...ec,lpddr-props.yaml => jedec,memory-props.yaml} | 24 +-
.../devicetree/bindings/perf/st,stm32-ddr-pmu.yaml | 94 +++
MAINTAINERS | 7 +
arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +
arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +
arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 +
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 12 +
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 12 +
drivers/bus/stm32_etzpc.c | 3 +-
drivers/bus/stm32_firewall.c | 3 +-
drivers/bus/stm32_rifsc.c | 3 +-
drivers/clk/stm32/clk-stm32mp25.c | 40 +-
drivers/perf/Kconfig | 11 +
drivers/perf/Makefile | 1 +
drivers/perf/stm32_ddr_pmu.c | 896 +++++++++++++++++++++
{drivers => include/linux}/bus/stm32_firewall.h | 0
25 files changed, 1266 insertions(+), 34 deletions(-)
---
base-commit: 89be9a83ccf1f88522317ce02f854f30d6115c41
change-id: 20250526-ddrperfm-upstream-bf07f57775da
Best regards,
--
Clément Le Goffic <clement.legoffic@...s.st.com>
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