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Message-ID: <ef79b37e-8b63-4ccc-a739-994a119b95c9@oss.qualcomm.com>
Date: Wed, 23 Jul 2025 12:10:53 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Akhil P Oommen <akhilpo@....qualcomm.com>,
Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 10/17] drm/msm/a6xx: Poll AHB fence status in GPU IRQ
handler
On 7/20/25 2:16 PM, Akhil P Oommen wrote:
> Even though GX power domain is kept ON when there is a pending GPU
> interrupt, there is a small window of potential race with GMU where it
> may move the AHB fence to 'Drop' mode. Close this race window by polling
> for AHB fence to ensure that it is in 'Allow' mode.
>
> Signed-off-by: Akhil P Oommen <akhilpo@....qualcomm.com>
> ---
There's some more context in this commit message, please include some
of it:
commit 5e1b78bde04ca08ebc27031aba509565f7df348a
Author: Kyle Piefer <kpiefer@...eaurora.org>
Date: Thu Oct 19 13:22:10 2017 -0700
msm: kgsl: Prevent repeated FENCE stuck errors
If the AHB fence is in DROP mode when we enter the RBBM
interrupt handler, it is usually harmless. The GMU will
see the pending interrupt and abort power collapse, causing
the fence to be set back to ALLOW. Until this happens though,
we cannot proceed to read the IRQ status and write the clear
register because they are inaccessible.
Poll the fence status until it is ALLOW and we can proceed.
If we poll for too long and the fence is still stuck,
the GMU is probably hung. In this case print an error
message and give up.
<cut off tags so as not to confuse b4>
Konrad
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