linux-kernel - Re: [PATCH v4 3/7] x86/virt/tdx: Mark memory cache state incoherent when making SEAMCALL

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <322fed1cba5355ec3ab27ad721ff8142e9361aff.camel@intel.com>
Date: Wed, 23 Jul 2025 01:59:28 +0000
From: "Huang, Kai" <kai.huang@...el.com>
To: "Gao, Chao" <chao.gao@...el.com>
CC: "kvm@...r.kernel.org" <kvm@...r.kernel.org>, "ashish.kalra@....com"
	<ashish.kalra@....com>, "Hansen, Dave" <dave.hansen@...el.com>,
	"thomas.lendacky@....com" <thomas.lendacky@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"mingo@...hat.com" <mingo@...hat.com>, "dwmw@...zon.co.uk"
	<dwmw@...zon.co.uk>, "pbonzini@...hat.com" <pbonzini@...hat.com>,
	"seanjc@...gle.com" <seanjc@...gle.com>, "tglx@...utronix.de"
	<tglx@...utronix.de>, "kas@...nel.org" <kas@...nel.org>, "Chatre, Reinette"
	<reinette.chatre@...el.com>, "Yamahata, Isaku" <isaku.yamahata@...el.com>,
	"nik.borisov@...e.com" <nik.borisov@...e.com>, "hpa@...or.com"
	<hpa@...or.com>, "peterz@...radead.org" <peterz@...radead.org>,
	"sagis@...gle.com" <sagis@...gle.com>, "Chen, Farrah"
	<farrah.chen@...el.com>, "Edgecombe, Rick P" <rick.p.edgecombe@...el.com>,
	"bp@...en8.de" <bp@...en8.de>, "x86@...nel.org" <x86@...nel.org>, "Williams,
 Dan J" <dan.j.williams@...el.com>
Subject: Re: [PATCH v4 3/7] x86/virt/tdx: Mark memory cache state incoherent
 when making SEAMCALL

On Tue, 2025-07-22 at 22:52 +0800, Gao, Chao wrote:
> > +static __always_inline u64 do_seamcall(sc_func_t func, u64 fn,
> > +				       struct tdx_module_args *args)
> > +{
> > +	u64 ret;
> > +
> > +	lockdep_assert_preemption_disabled();
> > +
> > +	/*
> > +	 * SEAMCALLs are made to the TDX module and can generate dirty
> > +	 * cachelines of TDX private memory.  Mark cache state incoherent
> > +	 * so that the cache can be flushed during kexec.
> > +	 *
> > +	 * This needs to be done before actually making the SEAMCALL,
> > +	 * because kexec-ing CPU could send NMI to stop remote CPUs,
> > +	 * in which case even disabling IRQ won't help here.
> > +	 */
> > +	this_cpu_write(cache_state_incoherent, true);
> > +
> > +	ret = func(fn, args);
> > +
> > +	return ret;
> 
> @ret can be dropped here. Just
> 
> 	return func(fn, args);
> 
> should work.

Yeah thanks will do.

> 
> And tracking cache incoherent state at the per-CPU level seems to add
> unnecessary complexity. It requires a new do_seamcall() wrapper, setting the
> flag on every seamcall rather than just the first one (I'm not concerned about
> performance; it just feels silly), and using preempt_disable()/enable(). In my
> view, per-CPU tracking at most saves a WBINVD on a CPU that never runs
> SEAMCALLs during KEXEC, which is quite marginal. Did I miss any other benefits?

The cache state is percpu thus a percpu boolean is a natural fit.  Besides
the benefit you mentioned, it fits better if there are other cases which
could also lead to an incoherent state:

https://lore.kernel.org/lkml/eb2e3b02-cf5e-4848-8f1d-9f3af8f9c96b@intel.com/

Setting the boolean in the SEAMCALL common code makes the logic quite
simple:

  If you ever do a SEAMCALL, mark the cache in incoherent state.

Please see Dave's comment here:

https://lore.kernel.org/lkml/31e17bc8-2e9e-4e93-a912-3d54826e59d0@intel.com/

The new code around the common SEAMCALL is pretty marginal comparing to
the SEAMCALL itself (as you said), and it's pretty straightforward, i.e.,
logically less error prone IMHO, so I am not seeing it silly.