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Message-ID: <20250724142144.776992-1-fabio.m.de.francesco@linux.intel.com>
Date: Thu, 24 Jul 2025 16:20:30 +0200
From: "Fabio M. De Francesco" <fabio.m.de.francesco@...ux.intel.com>
To: linux-cxl@...r.kernel.org
Cc: Davidlohr Bueso <dave@...olabs.net>,
Jonathan Cameron <jonathan.cameron@...wei.com>,
Dave Jiang <dave.jiang@...el.com>,
Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
Robert Richter <rrichter@....com>,
ming.li@...omail.com,
linux-kernel@...r.kernel.org,
"Fabio M. De Francesco" <fabio.m.de.francesco@...ux.intel.com>
Subject: [PATCH 0/4 v4] cxl/core: Enable Region creation/attach on x86 with LMH
The CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host
Physical Address (HPA) windows that are associated with each CXL Host
Bridge. Each window represents a contiguous HPA that may be interleaved
with one or more targets (CXL v3.1 - 9.18.1.3).
The Low Memory Hole (LMH) of x86 is a range of addresses of physical low
memory to which systems cannot send transactions. On those systems, BIOS
publishes CFMWS which communicate the active System Physical Address (SPA)
ranges that map to a subset of the Host Physical Address (HPA) ranges. The
SPA range trims out the hole, and capacity in the endpoint is lost with no
SPA to map to CXL HPA in that hole.
In the early stages of CXL Regions construction and attach on platforms
with Low Memory Holes, the driver fails and returns an error because it
expects that the CXL Endpoint Decoder range is a subset of the Root
Decoder's (SPA >= HPA). On x86 with LMH's, it happens that SPA < HPA.
Therefore, detect x86 Low Memory Holes, match CXL Root and Endpoint
Decoders or already made CXL Regions and Decoders to allow the
construction of new CXL Regions and the attachment of Endpoint Decoders,
even if SPA < HPA. If needed because of LMH's, adjust the Endpoint Decoder
range end to match Root Decoder's.
- Patch 1/4 changes the calling conventions of three match_*_by_range()
helpers in preparation of 3/4.
- Patch 2/4 Introduces helpers to detect LMH's and also one to adjust
the HPA range end for CXL Regions construction.
- Patch 3/4 enables CXL Regions construction and Endpoint Decoders
attachment by matching Root Decoders or Regions with Endpoint
Decoders, adjusting Endpoint Decoders HPA range end, and relaxing
constraints while Endpoints decoders' attachment.
- Patch 4/4 simulates a LMH for the CXL tests on patched CXL driver.
Many thanks to Alison, Dan, Dave and Ira for their help.
Commenting on v1, Alison wrote a couple of observations on what users
will see. I suggest anyone interested to see how this series affect
users to take a look at her observations.[0] Thank you!
Changes for v4:
Re-base on top of
"cxl: Address translation support, part 1: Cleanups and refactoring";[1]
Drop no more necessary 2/4;
Drop collected tags because of major changes throughout the series.
1/3 - Adjust Endpoint Decoders dpa_res->end (Alison) [2]
3/3 - Use weak/strong mechanism (Dan) [3]
Changes for v3:
Re-base the series on cxl/next.
1/4 - 2/4:
Constify local variables.
3/4:
Call arch_match_region() from region_res_match_cxl_range().
4/4:
arch_match_region() - Check that region end is under start + 4G;
arch_match_spa() - Check that SPA range start is cfmws_range_start.
v3 - https://lore.kernel.org/linux-cxl/20250314113708.759808-1-fabio.m.de.francesco@linux.intel.com/
v2 - https://lore.kernel.org/linux-cxl/20250114203432.31861-1-fabio.m.de.francesco@linux.intel.com/
v1 - https://lore.kernel.org/all/20241122155226.2068287-1-fabio.m.de.francesco@linux.intel.com/
[0] - https://lore.kernel.org/all/Z0Tzif55CcHuujJ-@aschofie-mobl2.lan/
[1] - https://lore.kernel.org/linux-cxl/20250509150700.2817697-1-rrichter@amd.com/
[2] - https://lore.kernel.org/linux-cxl/Z9tzZkn1rqd2Uk_6@aschofie-mobl2.lan/
[3] - https://lore.kernel.org/linux-cxl/67ee07cd4f8ec_1c2c6294d5@dwillia2-xfh.jf.intel.com.notmuch/
Fabio M. De Francesco (4):
cxl/core: Change match_*_by_range() signatures
cxl/core: Add helpers to detect Low Memory Holes on x86
cxl/core: Enable Region creation on x86 with LMH
cxl/test: Simulate an x86 Low Memory Hole for tests
drivers/cxl/Kconfig | 5 ++
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/platform.c | 86 +++++++++++++++++++
drivers/cxl/core/platform.h | 32 +++++++
drivers/cxl/core/region.c | 113 ++++++++++++++++--------
tools/testing/cxl/Kbuild | 2 +
tools/testing/cxl/mock_platform.c | 137 ++++++++++++++++++++++++++++++
tools/testing/cxl/test/cxl.c | 10 +++
tools/testing/cxl/test/mock.h | 1 +
9 files changed, 352 insertions(+), 35 deletions(-)
create mode 100644 drivers/cxl/core/platform.c
create mode 100644 drivers/cxl/core/platform.h
create mode 100644 tools/testing/cxl/mock_platform.c
base-commit: acc2913692413df9d1
--
2.50.1
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