| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250724083914.61351-35-angelogioacchino.delregno@collabora.com>
Date: Thu, 24 Jul 2025 10:39:10 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: linux-mediatek@...ts.infradead.org,
robh@...nel.org
Cc: herbert@...dor.apana.org.au,
davem@...emloft.net,
krzk+dt@...nel.org,
conor+dt@...nel.org,
chunkuang.hu@...nel.org,
p.zabel@...gutronix.de,
airlied@...il.com,
simona@...ll.ch,
maarten.lankhorst@...ux.intel.com,
mripard@...nel.org,
tzimmermann@...e.de,
jassisinghbrar@...il.com,
mchehab@...nel.org,
matthias.bgg@...il.com,
angelogioacchino.delregno@...labora.com,
chunfeng.yun@...iatek.com,
vkoul@...nel.org,
kishon@...nel.org,
sean.wang@...nel.org,
linus.walleij@...aro.org,
lgirdwood@...il.com,
broonie@...nel.org,
andersson@...nel.org,
mathieu.poirier@...aro.org,
daniel.lezcano@...aro.org,
tglx@...utronix.de,
atenart@...nel.org,
jitao.shi@...iatek.com,
ck.hu@...iatek.com,
houlong.wei@...iatek.com,
kyrie.wu@...iatek.corp-partner.google.com,
andy.teng@...iatek.com,
tinghan.shen@...iatek.com,
jiaxin.yu@...iatek.com,
shane.chien@...iatek.com,
olivia.wen@...iatek.com,
granquet@...libre.com,
eugen.hristev@...aro.org,
arnd@...db.de,
sam.shih@...iatek.com,
jieyy.yang@...iatek.com,
frank-w@...lic-files.de,
mwalle@...nel.org,
fparent@...libre.com,
linux-crypto@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
linux-media@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-phy@...ts.infradead.org,
linux-gpio@...r.kernel.org,
linux-remoteproc@...r.kernel.org,
linux-sound@...r.kernel.org
Subject: [PATCH 34/38] arm64: dts: mediatek: mt8195: Fix ranges for jpeg enc/decoder nodes
The jpeg decoder main node is under the soc bus but currently has
no ranges or reg specified, while the children do, and this is
wrong in multiple aspects.
The very same is also valid for the jpeg encoder node.
Rename the decoder and encoder nodes to "jpeg-decoder@...40000"
and to "jpeg-encoder@...30000" respectively, and change their
children to use the newly defined ranges.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 30 +++++++++++++-----------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index dd065b1bf94a..35b10082bb89 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -3014,7 +3014,7 @@ venc: video-codec@...20000 {
#size-cells = <2>;
};
- jpgdec-master {
+ jpeg-decoder@...40000 {
compatible = "mediatek,mt8195-jpgdec";
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
@@ -3025,11 +3025,12 @@ jpgdec-master {
<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
#address-cells = <2>;
#size-cells = <2>;
- ranges;
+ ranges = <0 0 0 0x1a040000 0 0x20000>,
+ <1 0 0 0x1b040000 0 0x10000>;
- jpgdec@...40000 {
+ jpgdec@0,0 {
compatible = "mediatek,mt8195-jpgdec-hw";
- reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
+ reg = <0 0 0 0x10000>;/* JPGDEC_C0 */
iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
@@ -3042,9 +3043,9 @@ jpgdec@...40000 {
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
};
- jpgdec@...50000 {
+ jpgdec@0,10000 {
compatible = "mediatek,mt8195-jpgdec-hw";
- reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
+ reg = <0 0 0x10000 0x10000>;/* JPGDEC_C1 */
iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
@@ -3057,9 +3058,9 @@ jpgdec@...50000 {
power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
};
- jpgdec@...40000 {
+ jpgdec@1,0 {
compatible = "mediatek,mt8195-jpgdec-hw";
- reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
+ reg = <1 0 0 0x10000>;/* JPGDEC_C2 */
iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
<&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
@@ -3088,7 +3089,7 @@ vdosys0: syscon@...1a000 {
};
- jpgenc-master {
+ jpeg-encoder@...30000 {
compatible = "mediatek,mt8195-jpgenc";
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
@@ -3097,11 +3098,12 @@ jpgenc-master {
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
#address-cells = <2>;
#size-cells = <2>;
- ranges;
+ ranges = <0 0 0 0x1a030000 0 0x10000>,
+ <1 0 0 0x1b030000 0 0x10000>;
- jpgenc@...30000 {
+ jpgenc@0,0 {
compatible = "mediatek,mt8195-jpgenc-hw";
- reg = <0 0x1a030000 0 0x10000>;
+ reg = <0 0 0 0x10000>;
iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
<&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
@@ -3112,9 +3114,9 @@ jpgenc@...30000 {
power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
};
- jpgenc@...30000 {
+ jpgenc@1,0 {
compatible = "mediatek,mt8195-jpgenc-hw";
- reg = <0 0x1b030000 0 0x10000>;
+ reg = <1 0 0 0x10000>;
iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
--
2.50.1
Powered by blists - more mailing lists