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Message-ID: <20250725-gentle-otter-of-stamina-c8e47b@kuoka>
Date: Fri, 25 Jul 2025 09:50:06 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Michal Simek <michal.simek@....com>
Cc: linux-kernel@...r.kernel.org, monstr@...str.eu,
michal.simek@...inx.com, git@...inx.com, Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2] dt-bindings: interrupt-controller: Add missing Xilinx
INTC binding
On Thu, Jul 24, 2025 at 12:57:57PM +0200, Michal Simek wrote:
> Add missing description for AMD/Xilinx interrupt controller. The binding is
> used by Microblaze before dt-binding even existed but never been
> documented properly.
>
> IP acts as primary interrupt controller on Microblaze systems or can be
> used as secondary interrupt controller on ARM based systems like Zynq,
> ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on
> Microblaze-V (Risc-V) systems.
>
> Over the years IP exists in multiple variants based on attached bus as OPB,
> PLB or AXI that's why generic filename is used.
>
> Property xlnx,kind-of-intr is in hex because every bit position corresponds
> to interrupt line. Controller support mixing edge or level interrupts
> together and this is the property which distinguish them.
>
> Signed-off-by: Michal Simek <michal.simek@....com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Best regards,
Krzysztof
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