linux-kernel - Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks

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Message-ID: <54b617c1-bd1b-4244-b75d-57eaaa2c083d@oss.qualcomm.com>
Date: Fri, 25 Jul 2025 11:30:57 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks

On 7/24/25 10:18 AM, Krzysztof Kozlowski wrote:
> On Wed, Jul 23, 2025 at 10:38:48PM +0200, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>>
>> The SM8750 features a "traditional" GPU_CC block, much of which is
>> controlled through the GMU microcontroller. Additionally, there's
>> an separate GX_CC block, where the GX GDSC is moved.
>>
>> Add bindings to accommodate for that.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>> ---
>>  .../bindings/clock/qcom,sm8450-gpucc.yaml          |  5 ++
>>  .../bindings/clock/qcom,sm8750-gxcc.yaml           | 61 ++++++++++++++++++++++
>>  include/dt-bindings/clock/qcom,sm8750-gpucc.h      | 53 +++++++++++++++++++
>>  3 files changed, 119 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
>> index 02968632fb3af34d6b3983a6a24aa742db1d59b1..d1b3557ab344b071d16dba4d5c6a267b7ab70573 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
>> @@ -20,6 +20,7 @@ description: |
>>      include/dt-bindings/clock/qcom,sm8550-gpucc.h
>>      include/dt-bindings/reset/qcom,sm8450-gpucc.h
>>      include/dt-bindings/reset/qcom,sm8650-gpucc.h
>> +    include/dt-bindings/reset/qcom,sm8750-gpucc.h
>>      include/dt-bindings/reset/qcom,x1e80100-gpucc.h
>>  
>>  properties:
>> @@ -31,6 +32,7 @@ properties:
>>        - qcom,sm8475-gpucc
>>        - qcom,sm8550-gpucc
>>        - qcom,sm8650-gpucc
>> +      - qcom,sm8750-gpucc
>>        - qcom,x1e80100-gpucc
>>        - qcom,x1p42100-gpucc
>>  
>> @@ -40,6 +42,9 @@ properties:
>>        - description: GPLL0 main branch source
>>        - description: GPLL0 div branch source
>>  
>> +  power-domains:
>> +    maxItems: 1
> 
> This should be a different binding or you need to restrict other
> variants here.

Actually looks like this is the same case as the recent videocc changes
(15 year old technical debt catching up to us..)

I'll send a mass-fixup for this.

Some platforms require 2 and some require 3 entries here. Do I have to
restrict them very specifically, or can I do:

power-domains:
  description:
    Power domains required for the clock controller to operate
  minItems: 2
  items:
    - description: CX power domain
    - description: MX power domain
    - description: MXC power domain

?

Konrad