linux-kernel - [PATCH v7 2/3] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy

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Message-Id: <20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com>
Date: Fri, 25 Jul 2025 18:22:30 +0800
From: Ziyue Zhang <ziyue.zhang@....qualcomm.com>
To: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
        krzk+dt@...nel.org, conor+dt@...nel.org, jingoohan1@...il.com,
        mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
        bhelgaas@...gle.com, johan+linaro@...nel.org, vkoul@...nel.org,
        kishon@...nel.org, neil.armstrong@...aro.org, abel.vesa@...aro.org,
        kw@...ux.com
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        linux-phy@...ts.infradead.org, qiang.yu@....qualcomm.com,
        quic_krichai@...cinc.com, quic_vbadigan@...cinc.com,
        Ziyue Zhang <ziyue.zhang@....qualcomm.com>
Subject: [PATCH v7 2/3] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy

The gcc_aux_clk is used by the PCIe Root Complex (RC) and is not required
by the PHY. The correct clock for the PHY is gcc_phy_aux_clk, which this
patch uses to replace the incorrect reference.

The distinction between AUX_CLK and PHY_AUX_CLK is important: AUX_CLK is
typically used by the controller, while PHY_AUX_CLK is required by certain
PHYs—particularly Gen4 QMP PHYs—for internal operations such as clock
gating and power management. Some non-Gen4 Qualcomm PHYs also use
PHY_AUX_CLK, but they do not require AUX_CLK.

This change ensures proper clock configuration and avoids unnecessary
dependencies.

Signed-off-by: Ziyue Zhang <ziyue.zhang@....qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 28 +++++++++++++++------------
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9997a29901f5..39a4f59d8925 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7707,16 +7707,18 @@ pcie0_phy: phy@...4000 {
 		compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
 		reg = <0x0 0x1c04000 0x0 0x2000>;
 
-		clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+		clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
 			 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 			 <&gcc GCC_PCIE_CLKREF_EN>,
 			 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
 			 <&gcc GCC_PCIE_0_PIPE_CLK>,
-			 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
-			 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
-
-		clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
-			      "pipediv2", "phy_aux";
+			 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
+		clock-names = "aux",
+			      "cfg_ahb",
+			      "ref",
+			      "rchng",
+			      "pipe",
+			      "pipediv2";
 
 		assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
 		assigned-clock-rates = <100000000>;
@@ -7873,16 +7875,18 @@ pcie1_phy: phy@...4000 {
 		compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
 		reg = <0x0 0x1c14000 0x0 0x4000>;
 
-		clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+		clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
 			 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 			 <&gcc GCC_PCIE_CLKREF_EN>,
 			 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
 			 <&gcc GCC_PCIE_1_PIPE_CLK>,
-			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
-			 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
-
-		clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
-			      "pipediv2", "phy_aux";
+			 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>;
+		clock-names = "aux",
+			      "cfg_ahb",
+			      "ref",
+			      "rchng",
+			      "pipe",
+			      "pipediv2";
 
 		assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
 		assigned-clock-rates = <100000000>;
-- 
2.34.1