linux-kernel - Re: [PATCH 23/38] arm64: dts: mediatek: mt7986a: Fix PCI-Express T-PHY node address

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAC=S1njhu11nHpyMULbK6PE-BLrBMq+d397pDU6gBzgo7xivXg@mail.gmail.com>
Date: Fri, 25 Jul 2025 18:43:57 +0800
From: Fei Shao <fshao@...omium.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: linux-mediatek@...ts.infradead.org, robh@...nel.org, 
	daniel.lezcano@...aro.org, mwalle@...nel.org, devicetree@...r.kernel.org, 
	linus.walleij@...aro.org, linux-remoteproc@...r.kernel.org, 
	dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org, 
	olivia.wen@...iatek.com, shane.chien@...iatek.com, linux-gpio@...r.kernel.org, 
	linux-phy@...ts.infradead.org, airlied@...il.com, simona@...ll.ch, 
	herbert@...dor.apana.org.au, jassisinghbrar@...il.com, jiaxin.yu@...iatek.com, 
	andy.teng@...iatek.com, chunfeng.yun@...iatek.com, jieyy.yang@...iatek.com, 
	chunkuang.hu@...nel.org, conor+dt@...nel.org, jitao.shi@...iatek.com, 
	p.zabel@...gutronix.de, arnd@...db.de, kishon@...nel.org, 
	kyrie.wu@...iatek.corp-partner.google.com, maarten.lankhorst@...ux.intel.com, 
	tinghan.shen@...iatek.com, mripard@...nel.org, ck.hu@...iatek.com, 
	broonie@...nel.org, eugen.hristev@...aro.org, houlong.wei@...iatek.com, 
	matthias.bgg@...il.com, tglx@...utronix.de, mchehab@...nel.org, 
	linux-arm-kernel@...ts.infradead.org, granquet@...libre.com, 
	sam.shih@...iatek.com, mathieu.poirier@...aro.org, fparent@...libre.com, 
	andersson@...nel.org, sean.wang@...nel.org, linux-sound@...r.kernel.org, 
	lgirdwood@...il.com, vkoul@...nel.org, linux-crypto@...r.kernel.org, 
	tzimmermann@...e.de, atenart@...nel.org, krzk+dt@...nel.org, 
	linux-media@...r.kernel.org, davem@...emloft.net
Subject: Re: [PATCH 23/38] arm64: dts: mediatek: mt7986a: Fix PCI-Express
 T-PHY node address

On Thu, Jul 24, 2025 at 5:49 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> The PCIe TPHY is under the soc bus, which provides MMIO, and all
> nodes under that must use the bus, otherwise those would clearly
> be out of place.
>
> Add ranges to the PCIe tphy and assign the address to the main
> node to silence a dtbs_check warning, and fix the children to
> use the MMIO range of t-phy.
>
> Fixes: 963c3b0c47ec ("arm64: dts: mediatek: fix t-phy unit name")
> Fixes: 918aed7abd2d ("arm64: dts: mt7986: add pcie related device nodes")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

Reviewed-by: Fei Shao <fshao@...omium.org>

> ---
>  arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> index 559990dcd1d1..3211905b6f86 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
> @@ -428,16 +428,16 @@ pcie_intc: interrupt-controller {
>                         };
>                 };
>
> -               pcie_phy: t-phy {
> +               pcie_phy: t-phy@...00000 {
>                         compatible = "mediatek,mt7986-tphy",
>                                      "mediatek,generic-tphy-v2";
> -                       ranges;
> -                       #address-cells = <2>;
> -                       #size-cells = <2>;
> +                       ranges = <0 0 0x11c00000 0x20000>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
>                         status = "disabled";
>
> -                       pcie_port: pcie-phy@...00000 {
> -                               reg = <0 0x11c00000 0 0x20000>;
> +                       pcie_port: pcie-phy@0 {
> +                               reg = <0 0x20000>;
>                                 clocks = <&clk40m>;
>                                 clock-names = "ref";
>                                 #phy-cells = <1>;
> --
> 2.50.1
>
>