| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250728-topic-gpucc_power_plumbing-v1-3-09c2480fe3e6@oss.qualcomm.com>
Date: Mon, 28 Jul 2025 18:16:03 +0200
From: Konrad Dybcio <konradybcio@...nel.org>
To: Ulf Hansson <ulf.hansson@...aro.org>,
Johan Hovold <johan+linaro@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Taniya Das <taniya.das@....qualcomm.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Taniya Das <quic_tdas@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>,
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>,
Dmitry Baryshkov <lumag@...nel.org>, cros-qcom-dts-watchers@...omium.org,
Douglas Anderson <dianders@...omium.org>, Vinod Koul <vkoul@...nel.org>,
Richard Acayan <mailingradian@...il.com>,
Andy Gross <andy.gross@...aro.org>, Ajit Pandey <quic_ajipan@...cinc.com>,
Luca Weiss <luca.weiss@...rphone.com>, Jonathan Marek <jonathan@...ek.ca>,
Neil Armstrong <neil.armstrong@...aro.org>,
Jagadeesh Kona <quic_jkona@...cinc.com>,
Akhil P Oommen <akhilpo@....qualcomm.com>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: [PATCH RFC 03/24] dt-bindings: clock: qcom,gpucc: Merge in
sm8450-gpucc.yaml
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
The only difference is the requirement of clock-names, and only for
legacy reasons.
Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 42 +++++++++++-
.../bindings/clock/qcom,sm8450-gpucc.yaml | 75 ----------------------
2 files changed, 39 insertions(+), 78 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
index 4cdff6161bf0b17526cc62b67d9c95086240fe46..5053d71f918bb28c504746f68e782ca719051f63 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
@@ -9,37 +9,55 @@ title: Qualcomm Graphics Clock & Reset Controller
maintainers:
- Taniya Das <quic_tdas@...cinc.com>
- Imran Shaik <quic_imrashai@...cinc.com>
+ - Konrad Dybcio <konradybcio@...nel.org>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
- include/dt-bindings/clock/qcom,gpucc-sdm845.h
+ include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,gpucc-sa8775p.h
include/dt-bindings/clock/qcom,gpucc-sc7180.h
include/dt-bindings/clock/qcom,gpucc-sc7280.h
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
+ include/dt-bindings/clock/qcom,gpucc-sdm845.h
include/dt-bindings/clock/qcom,gpucc-sm6350.h
include/dt-bindings/clock/qcom,gpucc-sm8150.h
include/dt-bindings/clock/qcom,gpucc-sm8250.h
include/dt-bindings/clock/qcom,gpucc-sm8350.h
include/dt-bindings/clock/qcom,qcs8300-gpucc.h
+ include/dt-bindings/clock/qcom,sar2130p-gpucc.h
+ include/dt-bindings/clock/qcom,sm4450-gpucc.h
+ include/dt-bindings/clock/qcom,sm8450-gpucc.h
+ include/dt-bindings/clock/qcom,sm8550-gpucc.h
+ include/dt-bindings/reset/qcom,sm8450-gpucc.h
+ include/dt-bindings/reset/qcom,sm8650-gpucc.h
+ include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
enum:
+ - qcom,milos-gpucc
- qcom,qcs8300-gpucc
- - qcom,sdm845-gpucc
- qcom,sa8775p-gpucc
+ - qcom,sar2130p-gpucc
- qcom,sc7180-gpucc
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
- qcom,sc8280xp-gpucc
+ - qcom,sdm845-gpucc
+ - qcom,sm4450-gpucc
- qcom,sm6350-gpucc
- qcom,sm8150-gpucc
- qcom,sm8250-gpucc
- qcom,sm8350-gpucc
+ - qcom,sm8450-gpucc
+ - qcom,sm8475-gpucc
+ - qcom,sm8550-gpucc
+ - qcom,sm8650-gpucc
+ - qcom,x1e80100-gpucc
+ - qcom,x1p42100-gpucc
clocks:
items:
@@ -62,7 +80,6 @@ properties:
required:
- compatible
- clocks
- - clock-names
- '#power-domain-cells'
# Require that power-domains and vdd-gfx-supply are not both present
@@ -74,6 +91,25 @@ not:
allOf:
- $ref: qcom,gcc.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,qcs8300-gpucc
+ - qcom,sdm845-gpucc
+ - qcom,sa8775p-gpucc
+ - qcom,sc7180-gpucc
+ - qcom,sc7280-gpucc
+ - qcom,sc8180x-gpucc
+ - qcom,sc8280xp-gpucc
+ - qcom,sm6350-gpucc
+ - qcom,sm8150-gpucc
+ - qcom,sm8250-gpucc
+ - qcom,sm8350-gpucc
+ then:
+ required:
+ - clock-names
+
unevaluatedProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
deleted file mode 100644
index 44380f6f81368339c2b264bde4d8ad9a23baca72..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+++ /dev/null
@@ -1,75 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Graphics Clock & Reset Controller on SM8450
-
-maintainers:
- - Konrad Dybcio <konradybcio@...nel.org>
-
-description: |
- Qualcomm graphics clock control module provides the clocks, resets and power
- domains on Qualcomm SoCs.
-
- See also::
- include/dt-bindings/clock/qcom,milos-gpucc.h
- include/dt-bindings/clock/qcom,sar2130p-gpucc.h
- include/dt-bindings/clock/qcom,sm4450-gpucc.h
- include/dt-bindings/clock/qcom,sm8450-gpucc.h
- include/dt-bindings/clock/qcom,sm8550-gpucc.h
- include/dt-bindings/reset/qcom,sm8450-gpucc.h
- include/dt-bindings/reset/qcom,sm8650-gpucc.h
- include/dt-bindings/reset/qcom,x1e80100-gpucc.h
-
-properties:
- compatible:
- enum:
- - qcom,milos-gpucc
- - qcom,sar2130p-gpucc
- - qcom,sm4450-gpucc
- - qcom,sm8450-gpucc
- - qcom,sm8475-gpucc
- - qcom,sm8550-gpucc
- - qcom,sm8650-gpucc
- - qcom,x1e80100-gpucc
- - qcom,x1p42100-gpucc
-
- clocks:
- items:
- - description: Board XO source
- - description: GPLL0 main branch source
- - description: GPLL0 div branch source
-
-required:
- - compatible
- - clocks
- - '#power-domain-cells'
-
-allOf:
- - $ref: qcom,gcc.yaml#
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,gcc-sm8450.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
-
- clock-controller@...0000 {
- compatible = "qcom,sm8450-gpucc";
- reg = <0 0x03d90000 0 0xa000>;
- clocks = <&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_GPU_GPLL0_CLK_SRC>,
- <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
- };
-...
--
2.50.1
Powered by blists - more mailing lists