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Message-ID: <20250729195137.GA658914-robh@kernel.org>
Date: Tue, 29 Jul 2025 14:51:37 -0500
From: Rob Herring <robh@...nel.org>
To: Herve Codina <herve.codina@...tlin.com>
Cc: Hoan Tran <hoan@...amperecomputing.com>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Saravana Kannan <saravanak@...gle.com>,
Serge Semin <fancer.lancer@...il.com>,
Phil Edworthy <phil.edworthy@...esas.com>,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
Miquel Raynal <miquel.raynal@...tlin.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH 5/6] soc: renesas: Add support for Renesas RZ/N1 GPIO
Interrupt Multiplexer
On Fri, Jul 25, 2025 at 05:26:14PM +0200, Herve Codina wrote:
> On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
> interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
> order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
>
> The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
> IRQ lines out of the 96 available to wire them to the GIC input lines.
>
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
> ---
> drivers/soc/renesas/Kconfig | 4 +
> drivers/soc/renesas/Makefile | 1 +
> drivers/soc/renesas/rzn1_irqmux.c | 169 ++++++++++++++++++++++++++++++
> 3 files changed, 174 insertions(+)
> create mode 100644 drivers/soc/renesas/rzn1_irqmux.c
>
> diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> index fbc3b69d21a7..9e8ac33052fb 100644
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -58,6 +58,7 @@ config ARCH_RZN1
> select PM
> select PM_GENERIC_DOMAINS
> select ARM_AMBA
> + select RZN1_IRQMUX
>
> if ARM && ARCH_RENESAS
>
> @@ -435,6 +436,9 @@ config PWC_RZV2M
> config RST_RCAR
> bool "Reset Controller support for R-Car" if COMPILE_TEST
>
> +config RZN1_IRQMUX
> + bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
> +
> config SYSC_RZ
> bool "System controller for RZ SoCs" if COMPILE_TEST
>
> diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
> index 3bdcc6a395d5..daa932c7698d 100644
> --- a/drivers/soc/renesas/Makefile
> +++ b/drivers/soc/renesas/Makefile
> @@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o
> # Family
> obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o
> obj-$(CONFIG_RST_RCAR) += rcar-rst.o
> +obj-$(CONFIG_RZN1_IRQMUX) += rzn1_irqmux.o
> obj-$(CONFIG_SYSC_RZ) += rz-sysc.o
> diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_irqmux.c
> new file mode 100644
> index 000000000000..37e41c2b9104
> --- /dev/null
> +++ b/drivers/soc/renesas/rzn1_irqmux.c
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * RZ/N1 GPIO Interrupt Multiplexer
> + *
> + * Copyright 2025 Schneider Electric
> + * Author: Herve Codina <herve.codina@...tlin.com>
> + */
> +
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +
> +#define IRQMUX_MAX_IRQS 8
> +
> +static int irqmux_is_phandle_args_equal(const struct of_phandle_args *a,
> + const struct of_phandle_args *b)
> +{
> + int i;
> +
> + if (a->np != b->np)
> + return false;
> +
> + if (a->args_count != b->args_count)
> + return false;
> +
> + for (i = 0; i < a->args_count; i++) {
> + if (a->args[i] != b->args[i])
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static int irqmux_find_interrupt_index(struct device *dev, struct device_node *np,
> + const struct of_phandle_args *expected_irq)
> +{
> + struct of_phandle_args out_irq;
> + bool is_equal;
> + int ret;
> + int i;
> +
> + for (i = 0; i < IRQMUX_MAX_IRQS; i++) {
> + ret = of_irq_parse_one(np, i, &out_irq);
I don't really want more users of this... More below.
> + if (ret)
> + return ret;
> +
> + is_equal = irqmux_is_phandle_args_equal(expected_irq, &out_irq);
> + of_node_put(out_irq.np);
> + if (is_equal)
> + return i;
> + }
> +
> + return -ENOENT;
> +}
> +
> +struct irqmux_cb_data {
> + struct device_node *np;
> + struct device *dev;
> + u32 __iomem *regs;
> +};
> +
> +static int irqmux_imap_cb(void *data, const __be32 *imap,
> + const struct of_phandle_args *parent_args)
> +{
> + struct irqmux_cb_data *priv = data;
> + u32 src_hwirq;
> + int index;
> +
> + /*
> + * The child #address-cells is 0. Already checked in irqmux_setup().
> + * The first value in imap is the src_hwirq
> + */
> + src_hwirq = be32_to_cpu(*imap);
The iterator should take care of the endianness conversion.
> +
> + /*
> + * Get the index in our interrupt array that matches the parent in the
> + * interrupt-map
> + */
> + index = irqmux_find_interrupt_index(priv->dev, priv->np, parent_args);
> + if (index < 0)
> + return dev_err_probe(priv->dev, index, "output interrupt not found\n");
> +
> + dev_info(priv->dev, "interrupt %u mapped to output interrupt[%u]\n",
> + src_hwirq, index);
Do you even need "interrupts"? Just make the "interrupt-map" index
important and correspond to the hw index. That would greatly simplify
all this.
> +
> + /*
> + * Our interrupt array items matches 1:1 the interrupt lines that could
> + * be configured by registers (same order, same number).
> + * Configure the related register with the src hwirq retrieved from the
> + * interrupt-map.
> + */
> + writel(src_hwirq, priv->regs + index);
> +
> + return 0;
> +}
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