lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAAQKjZP12LZPHcPo1ztvKq6Vts=Mp0o5NyJfdCZZoMB633wynQ@mail.gmail.com>
Date: Tue, 29 Jul 2025 16:35:29 +0900
From: Inki Dae <daeinki@...il.com>
To: Kaustabh Chakraborty <kauschluss@...root.org>
Cc: Jagan Teki <jagan@...rulasolutions.com>, Marek Szyprowski <m.szyprowski@...sung.com>, 
	Andrzej Hajda <andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>, 
	Robert Foss <rfoss@...nel.org>, Laurent Pinchart <Laurent.pinchart@...asonboard.com>, 
	Jonas Karlman <jonas@...boo.se>, Jernej Skrabec <jernej.skrabec@...il.com>, 
	Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>, 
	Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Seung-Woo Kim <sw0312.kim@...sung.com>, Kyungmin Park <kyungmin.park@...sung.com>, 
	Krzysztof Kozlowski <krzk@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>, 
	dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v3 00/13] Support for Exynos7870 DSIM bridge

Hi Kaustabh Chakraborty,

2025년 7월 7일 (월) 오전 3:26, Kaustabh Chakraborty <kauschluss@...root.org>님이 작성:
>
> This patch series introduces a lot of changes to the existing DSIM
> bridge driver, by introdcing new registers and making register offsets
> configurable for different SoCs. These preliminary changes are followed
> by the introduction of support for Exynos7870's DSIM IP block.
>
> Work is heavily inspired and only possible due to Samsung's vendor
> kernel sources. Testing has been done with Samsung Galaxy J7 Prime
> (samsung-on7xelte), Samsung Galaxy A2 Core (samsung-a2corelte), and
> Samsung Galaxy J6 (samsung-j6lte), all with DSI video mode panels.

Patches 1 through 12 have been merged into the exynos-drm-misc-next branch.
- Patch 9 was merged as-is. If you decide to accept my suggestion and
submit a revised version later, I will apply it on top of the existing
patch.
- Patch 10 was also merged without modification. Although it includes
a behavioral change (removal of the fallback to pll_clk), I don’t
foresee any issues. If any problems arise, I’ll revert it.

And patch 13 has been merged into the exynos-drm-next branch.

Thanks,
Inki Dae

>
> Signed-off-by: Kaustabh Chakraborty <kauschluss@...root.org>
> ---
> Changes in v3:
> - support both legacy STATUS and LINK_STATUS & DPHY_STATUS split (daeinki)
> - Link to v2: https://lore.kernel.org/r/20250627-exynos7870-dsim-v2-0-1433b67378d3@disroot.org
>
> Changes in v2:
> - added commit to isolate clock names for each variant
> - replaced clock names with generic ones (krzk)
> - added maxItems to clocks property in dtschema (krzk)
> - Link to v1: https://lore.kernel.org/r/20250612-exynos7870-dsim-v1-0-1a330bca89df@disroot.org
>
> ---
> Kaustabh Chakraborty (13):
>       drm/bridge: samsung-dsim: support separate LINK and DPHY status registers
>       drm/bridge: samsung-dsim: add SFRCTRL register
>       drm/bridge: samsung-dsim: add flag to control header FIFO wait
>       drm/bridge: samsung-dsim: allow configuring bits and offsets of CLKCTRL register
>       drm/bridge: samsung-dsim: allow configuring the MAIN_VSA offset
>       drm/bridge: samsung-dsim: allow configuring the VIDEO_MODE bit
>       drm/bridge: samsung-dsim: allow configuring PLL_M and PLL_S offsets
>       drm/bridge: samsung-dsim: allow configuring the PLL_STABLE bit
>       drm/bridge: samsung-dsim: increase timeout value for PLL_STABLE
>       drm/bridge: samsung-dsim: add ability to define clock names for every variant
>       dt-bindings: samsung,mipi-dsim: document exynos7870 DSIM compatible
>       drm/bridge: samsung-dsim: add driver support for exynos7870 DSIM bridge
>       drm/exynos: dsi: add support for exynos7870
>
>  .../bindings/display/bridge/samsung,mipi-dsim.yaml |  27 ++
>  drivers/gpu/drm/bridge/samsung-dsim.c              | 353 ++++++++++++++++-----
>  drivers/gpu/drm/exynos/exynos_drm_dsi.c            |   9 +
>  include/drm/bridge/samsung-dsim.h                  |  16 +-
>  4 files changed, 317 insertions(+), 88 deletions(-)
> ---
> base-commit: 26ffb3d6f02cd0935fb9fa3db897767beee1cb2a
> change-id: 20250523-exynos7870-dsim-f29d6eafca52
>
> Best regards,
> --
> Kaustabh Chakraborty <kauschluss@...root.org>
>
>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ