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Message-ID: <CA+V-a8tiNRontyNLXEZEtj+SyCm+gKe+0e1aV=pboWJHPOvDfw@mail.gmail.com>
Date: Tue, 29 Jul 2025 13:52:14 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Rob Herring <robh@...nel.org>, Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Linus Walleij <linus.walleij@...aro.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>,
Bartosz Golaszewski <brgl@...ev.pl>, linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>
Subject: Re: [PATCH v3 1/3] dt-bindings: pinctrl: renesas: document RZ/T2H and
RZ/N2H SoCs
Hi Rob,
Thank you for the review, sorry for the late reply.
On Tue, Jul 8, 2025 at 8:55 PM Rob Herring <robh@...nel.org> wrote:
>
> On Mon, Jul 07, 2025 at 03:18:46PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Document the pin and GPIO controller IP for the Renesas RZ/T2H
> > (R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI
> > header file used by both the bindings and the driver.
> >
> > The RZ/T2H SoC supports 729 pins, while the RZ/N2H supports 576 pins.
> > Both share the same controller architecture; separate compatible
> > strings are added for each SoC to distinguish them.
> >
> > Co-developed-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> > v2->v3:
> > - Dropped refference to gpio.txt instead pointed to
> > in include/dt-bindings/gpio/gpio.h.
> >
> > v1->v2:
> > - Added a new DT binding file
> > ---
> > .../pinctrl/renesas,rzt2h-pinctrl.yaml | 132 ++++++++++++++++++
> > .../pinctrl/renesas,r9a09g077-pinctrl.h | 22 +++
> > 2 files changed, 154 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml
> > create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml
> > new file mode 100644
> > index 000000000000..ead5ab7e7ebb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml
> > @@ -0,0 +1,132 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/renesas,rzt2h-pinctrl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/T2H Pin and GPIO controller
> > +
> > +maintainers:
> > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > +
> > +description:
> > + The Renesas RZ/T2H SoC features a combined Pin and GPIO controller.
> > + Pin multiplexing and GPIO configuration is performed on a per-pin basis.
> > + Each port features up to 8 pins, each of them configurable for GPIO function
> > + (port mode) or in alternate function mode.
> > + Up to 8 different alternate function modes exist for each single pin.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - renesas,r9a09g077-pinctrl # RZ/T2H
> > + - renesas,r9a09g087-pinctrl # RZ/N2H
> > +
> > + reg:
> > + minItems: 1
> > + items:
> > + - description: Non-safety I/O Port base
> > + - description: Safety I/O Port safety region base
> > + - description: Safety I/O Port Non-safety region base
> > +
> > + reg-names:
> > + minItems: 1
> > + items:
> > + - const: nsr
> > + - const: srs
> > + - const: srn
> > +
> > + gpio-controller: true
> > +
> > + '#gpio-cells':
> > + const: 2
> > + description:
> > + The first cell contains the global GPIO port index, constructed using the
> > + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
> > + (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
> > + flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.
> > +
> > + gpio-ranges:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > +additionalProperties:
> > + anyOf:
> > + - type: object
> > + additionalProperties: false
> > + allOf:
> > + - $ref: pincfg-node.yaml#
> > + - $ref: pinmux-node.yaml#
> > +
> > + description:
> > + Pin controller client devices use pin configuration subnodes (children
> > + and grandchildren) for desired pin configuration.
> > + Client device subnodes use the below standard properties.
> > +
> > + properties:
> > + pinmux:
> > + description:
> > + Values are constructed from GPIO port number, pin number, and
> > + alternate function configuration number using the RZT2H_PORT_PINMUX()
> > + helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
> > + pins: true
> > + gpio-hog: true
> > + gpios: true
> > + input: true
> > + input-enable: true
> > + output-enable: true
> > + output-high: true
> > + output-low: true
> > + line-name: true
> > +
> > + - type: object
> > + additionalProperties:
> > + $ref: "#/additionalProperties/anyOf/0"
>
> Again, please define some common suffix or prefix for the node names.
> Any name is for existing bindings *only*.
>
> patternProperties:
> '-pins$':
> type: object
> ...
>
> '-state$':
> type: object
> additionalProperties:
> $ref: '#/patternProperties/-pins$'
>
> I don't care what prefixes you use here...
>
> (Note some regex's don't work as JSON pointers and then you would have
> to use a $defs section.)
>
Ok, I'll switch to patter properties like below. Ive added properties
for group/pins/hog
- group pattern, will include nodes with multiple pins node
- pins pattern, will contain single node
- hog pattern, will contain gpio hog node
Please let me know if the below approach is OK.
patternProperties:
'.*-group$':
type: object
description:
Pin controller client devices can organize pin configuration entries into
grouping nodes ending in "-group". These group nodes may contain multiple
child nodes each ending in "-pins" to configure distinct sets of pins.
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: >-
Pin configuration subnodes of a "-group" for desired pin settings.
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pinmux: true
pins: true
gpio-hog: true
gpios: true
input: true
input-enable: true
output-enable: true
output-high: true
output-low: true
line-name: true
additionalProperties: false
'-pins$':
type: object
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use the below standard properties.
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
properties:
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZT2H_PORT_PINMUX()
helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
pins: true
gpio-hog: true
gpios: true
input: true
input-enable: true
output-enable: true
output-high: true
output-low: true
line-name: true
additionalProperties: false
'-hog$':
type: object
description: GPIO hog node
required:
- gpio-hog
- gpios
properties:
gpio-hog: true
gpios: true
input: true
input-enable: true
output-enable: true
output-high: true
output-low: true
line-name: true
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- reg-names
- gpio-controller
- '#gpio-cells'
- gpio-ranges
- clocks
- power-domains
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
pinctrl@...c0000 {
compatible = "renesas,r9a09g077-pinctrl";
reg = <0x802c0000 0x2000>,
<0x812c0000 0x2000>,
<0x802b0000 0x2000>;
reg-names = "nsr", "srs", "srn";
clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
power-domains = <&cpg>;
sci_pins: serial0-pins {
pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
<RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
};
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZT2H_GPIO(39, 2) 0>;
output-high;
line-name = "sd1_pwr_en";
};
i2c0_pins: i2c0-pins {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
sdhi0_sd_pins: sd0-sd-group {
sd0-sd-ctrl-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
};
sd0-sd-data-pins {
pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
};
sd0-sd-tmp-pins {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
};
};
Cheers,
Prabhakar
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