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Message-Id: <20250729-topic-sm8x50-usb-flatten-v1-2-4be74a629136@linaro.org>
Date: Tue, 29 Jul 2025 16:58:18 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Neil Armstrong <neil.armstrong@...aro.org>
Subject: [PATCH 2/2] arm64: dts: qcom: sm8650: Flatten the USB nodes
Transition the USB controllers found in the SM8650 SoC to the newly
introduced, flattened representation of the Qualcomm USB block, i.e.
qcom,snps-dwc3, to show the end result.
The reg and interrupts properties from the usb child node are merged
with their counterpart in the outer node, remaining properties and child
nodes are simply moved.
Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 6 +--
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 6 +--
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +--
arch/arm64/boot/dts/qcom/sm8650.dtsi | 86 +++++++++++++++------------------
4 files changed, 46 insertions(+), 58 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index 259649d7dcd768ecf93c9473adc1738e7d715b6c..a00da76a60620b998973cab189f12eeaa0a448fa 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -1310,12 +1310,10 @@ &ufs_mem_phy {
*/
&usb_1 {
- status = "okay";
-};
-
-&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
+
+ status = "okay";
};
&usb_1_dwc3_hs {
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 8a957adbfb383411153506e46d4c9acfb02e3114..c67bbace27439ad67cfb247a88aec633f93f5a6d 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -857,12 +857,10 @@ &ufs_mem_phy {
*/
&usb_1 {
- status = "okay";
-};
-
-&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
+
+ status = "okay";
};
&usb_1_dwc3_hs {
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index 7552d5d3fb4020e61d47242b447c9ecbec5f8d55..081b7e40f5742120a611cbfa57a59dfb1dc19b9f 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -1293,12 +1293,10 @@ &ufs_mem_phy {
*/
&usb_1 {
- status = "okay";
-};
-
-&usb_1_dwc3 {
dr_mode = "otg";
usb-role-switch;
+
+ status = "okay";
};
&usb_1_dwc3_hs {
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index e14d3d778b71bbbd0c8fcc851eebc9df9ac09c31..0120b9c7432a945a204ed76a461a6d0f13875537 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5651,16 +5651,18 @@ usb_dp_qmpphy_dp_in: endpoint {
};
};
- usb_1: usb@...8800 {
- compatible = "qcom,sm8650-dwc3", "qcom,dwc3";
- reg = <0 0x0a6f8800 0 0x400>;
+ usb_1: usb@...0000 {
+ compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3";
+ reg = <0 0x0a600000 0 0x10000>;
- interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
+ interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
<&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "pwr_event",
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
"hs_phy_irq",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
@@ -5685,6 +5687,11 @@ usb_1: usb@...8800 {
resets = <&gcc GCC_USB30_PRIM_BCR>;
+ phys = <&usb_1_hsphy>,
+ <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
@@ -5692,59 +5699,46 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "usb-ddr",
"apps-usb";
+ iommus = <&apps_smmu 0x40 0>;
+
power-domains = <&gcc USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- status = "disabled";
-
- usb_1_dwc3: usb@...0000 {
- compatible = "snps,dwc3";
- reg = <0 0x0a600000 0 0xcd00>;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,usb2-gadget-lpm-disable;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,is-utmi-l1-suspend;
+ snps,usb3_lpm_capable;
+ snps,usb2-lpm-disable;
+ snps,has-lpm-erratum;
+ tx-fifo-resize;
- interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>;
-
- iommus = <&apps_smmu 0x40 0>;
-
- phys = <&usb_1_hsphy>,
- <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
- phy-names = "usb2-phy",
- "usb3-phy";
+ dma-coherent;
- snps,hird-threshold = /bits/ 8 <0x0>;
- snps,usb2-gadget-lpm-disable;
- snps,dis_u2_susphy_quirk;
- snps,dis_enblslpm_quirk;
- snps,dis-u1-entry-quirk;
- snps,dis-u2-entry-quirk;
- snps,is-utmi-l1-suspend;
- snps,usb3_lpm_capable;
- snps,usb2-lpm-disable;
- snps,has-lpm-erratum;
- tx-fifo-resize;
+ #address-cells = <1>;
+ #size-cells = <0>;
- dma-coherent;
+ status = "disabled";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- port@0 {
- reg = <0>;
+ port@0 {
+ reg = <0>;
- usb_1_dwc3_hs: endpoint {
- };
+ usb_1_dwc3_hs: endpoint {
};
+ };
- port@1 {
- reg = <1>;
+ port@1 {
+ reg = <1>;
- usb_1_dwc3_ss: endpoint {
- remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
- };
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
};
};
};
--
2.34.1
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