linux-kernel - [PATCH V1 3/3] arm64: dts: qcom: sm8750: Enable MCQ support for UFS controller

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Message-ID: <20250730082229.23475-4-quic_rdwivedi@quicinc.com>
Date: Wed, 30 Jul 2025 13:52:29 +0530
From: Ram Kumar Dwivedi <quic_rdwivedi@...cinc.com>
To: <mani@...nel.org>, <alim.akhtar@...sung.com>, <avri.altman@....com>,
        <bvanassche@....org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <andersson@...nel.org>,
        <konradybcio@...nel.org>, <agross@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <linux-scsi@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH V1 3/3] arm64: dts: qcom: sm8750: Enable MCQ support for UFS controller

From: Palash Kambar <quic_pkambar@...cinc.com>

Enable Multi-Circular Queue (MCQ) support for the UFS host controller
on the Qualcomm SM8750 platform by updating the device tree node. This
includes adding new register regions and specifying the MSI parent
required for MCQ operation.

MCQ is a modern queuing model for UFS that improves performance and
scalability by allowing multiple hardware queues. Although MCQ support
has existed in the UFS driver for several years, this patch enables it
via Device Tree for SM8750.

Changes:
- Add reg entries for mcq_sqd and mcq_vs regions.
- Define reg-names for the new regions.
- Specify msi-parent for interrupt routing.

Signed-off-by: Palash Kambar <quic_pkambar@...cinc.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 4643705021c6..401e510ee738 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3329,7 +3329,12 @@ ufs_mem_phy: phy@...0000 {
 
 		ufs_mem_hc: ufs@...4000 {
 			compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
-			reg = <0x0 0x01d84000 0x0 0x3000>;
+			reg = <0x0 0x01d84000 0x0 0x3000>,
+			      <0x0 0x1da5000 0x0 0x2000>,
+			      <0x0 0x1da4000 0x0 0x10>;
+			reg-names = "ufs_mem",
+				    "mcq_sqd",
+				    "mcq_vs";
 
 			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 
@@ -3363,11 +3368,12 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 					     "cpu-ufs";
 
 			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+
 			required-opps = <&rpmhpd_opp_nom>;
 
 			iommus = <&apps_smmu 0x60 0>;
 			dma-coherent;
-
+			msi-parent = <&gic_its 0x60>;
 			lanes-per-direction = <2>;
 
 			phys = <&ufs_mem_phy>;
-- 
2.50.1