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Message-ID: <aInqV5IEAN9LRvFV@hovoldconsulting.com>
Date: Wed, 30 Jul 2025 11:48:07 +0200
From: Johan Hovold <johan@...nel.org>
To: Ziyue Zhang <ziyue.zhang@....qualcomm.com>
Cc: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, jingoohan1@...il.com,
mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
bhelgaas@...gle.com, johan+linaro@...nel.org, vkoul@...nel.org,
kishon@...nel.org, neil.armstrong@...aro.org, abel.vesa@...aro.org,
kw@...ux.com, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
qiang.yu@....qualcomm.com, quic_krichai@...cinc.com,
quic_vbadigan@...cinc.com
Subject: Re: [PATCH v9 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy:
Update pcie phy bindings for qcs8300
On Fri, Jul 25, 2025 at 06:40:33PM +0800, Ziyue Zhang wrote:
> The gcc_aux_clk is not required by the PCIe PHY on qcs8300 and is not
> specified in the device tree node. Hence, move the qcs8300 phy
> compatibility entry into the list of PHYs that require six clocks.
>
> Removed the phy_aux clock from the PCIe PHY binding as it is no longer
> used by any instance.
>
> Fixes: e46e59b77a9e ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2")
>
> Signed-off-by: Ziyue Zhang <ziyue.zhang@....qualcomm.com>
> Acked-by: Rob Herring (Arm) <robh@...nel.org>
Reviewed-by: Johan Hovold <johan+linaro@...nel.org>
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