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Message-ID: <20250730101015.323964-1-manikandan.m@microchip.com>
Date: Wed, 30 Jul 2025 15:40:13 +0530
From: Manikandan Muralidharan <manikandan.m@...rochip.com>
To: <broonie@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <nicolas.ferre@...rochip.com>,
<alexandre.belloni@...tlin.com>, <claudiu.beznea@...on.dev>,
<ryan.wanner@...rochip.com>, <tudor.ambarus@...aro.org>,
<linux-spi@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
CC: <manikandan.m@...rochip.com>
Subject: [PATCH v2 1/3] spi: atmel: simplify MR register update in cs_activate()
simplified the MR register configuration by updating only the PCS field
using SPI_BFINS() instead of rewriting the entire register.
Avoids code duplication.
Signed-off-by: Manikandan Muralidharan <manikandan.m@...rochip.com>
---
changes in v2:
- Fixed mail threading
---
drivers/spi/spi-atmel.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 89a6b46cd319..409f544d8983 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -397,20 +397,10 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
* on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
*/
spi_writel(as, CSR0, asd->csr);
- if (as->caps.has_wdrbt) {
- spi_writel(as, MR,
- SPI_BF(PCS, ~(0x01 << chip_select))
- | SPI_BIT(WDRBT)
- | SPI_BIT(MODFDIS)
- | SPI_BIT(MSTR));
- } else {
- spi_writel(as, MR,
- SPI_BF(PCS, ~(0x01 << chip_select))
- | SPI_BIT(MODFDIS)
- | SPI_BIT(MSTR));
- }
mr = spi_readl(as, MR);
+ mr = SPI_BFINS(PCS, ~(0x01 << chip_select), mr);
+ spi_writel(as, MR, mr);
/*
* Ensures the clock polarity is valid before we actually
base-commit: 4b290aae788e06561754b28c6842e4080957d3f7
--
2.25.1
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