linux-kernel - RE: [PATCH RFT 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior

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Message-ID: 
 <TY7PR01MB14818EC396806B8EA7CE96AB09224A@TY7PR01MB14818.jpnprd01.prod.outlook.com>
Date: Wed, 30 Jul 2025 00:13:06 +0000
From: <nobuhiro1.iwamatsu@...hiba.co.jp>
To: <Frank.li@....com>
CC: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <lpieralisi@...nel.org>, <kwilczynski@...nel.org>, <mani@...nel.org>,
        <bhelgaas@...gle.com>, <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-pci@...r.kernel.org>
Subject: RE: [PATCH RFT 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges
 to reflect hardware behavior

Hi Frank,

> > > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > > b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > > index 39806f0ae5133..2a18aa93d4723 100644
> > > --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> > > @@ -147,7 +147,15 @@ soc {
> > >  		#size-cells = <2>;
> > >  		compatible = "simple-bus";
> > >  		interrupt-parent = <&gic>;
> > > -		ranges;
> > > +		ranges = /* register 1:1 map */
> > > +			 <0x0 0x24000000 0x0 0x24000000 0x0 0x10000000>,
> > > +			 /*
> > > +			  * bus fabric mask address bit 30 and 31 to 0
> > > +			  * before send to PCIe controller.
> > > +			  *
> > > +			  * PCIe map address 0 to cpu's 0x40000000
> > > +			  */
> > > +			 <0x0 0x00000000 0x0 0x40000000 0x0 0x40000000>;
> > >
> > >  		gic: interrupt-controller@...01000 {
> > >  			compatible = "arm,gic-400";
> > > @@ -481,7 +489,7 @@ pwm: pwm@...c0000 {
> > >  		pcie: pcie@...00000 {
> > >  			compatible = "toshiba,visconti-pcie";
> > >  			reg = <0x0 0x28400000 0x0 0x00400000>,
> > > -			      <0x0 0x70000000 0x0 0x10000000>,
> > > +			      <0x0 0x30000000 0x0 0x10000000>,
> >
> > If my understanding is correct, this setting conflicts with the
> > address space this patch changed ranges above. Therefore, it does not work.
> >
> > 0x24000000 + 0x10000000 > 0x30000000
> 
> You are right.  Address map should only happen at pci fabic.
> 
> So we should not touch soc's ranges.
> 
> soc {
> 	...
> 
> 	pci-bus {
> 		 ranges = /* register 1:1 map */
>                  <0x0 0x24000000 0x0 0x24000000 0x0 0x10000000>,
>                  /*
>                   * bus fabric mask address bit 30 and 31 to 0
>                   * before send to PCIe controller.
>                   *
>                   * PCIe map address 0 to cpu's 0x40000000
>                   */
>                  <0x0 0x00000000 0x0 0x40000000 0x0 0x40000000>;
> 
> 
> 		pci@...4000000 {
> 			...
> 		}
> 	}
> }

Does this mean that a pci subbus is defined under soc, right?

> 
> Do you need me send v2 for your test?
> 

I will create a patch, so please review it.
Thank you.

> Frank

Best regards,
  Nobuhiro