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Message-Id: <6e34b4af-dff9-4360-b3da-c95ca7c740c9@app.fastmail.com>
Date: Thu, 31 Jul 2025 21:01:17 +0200
From: "Arnd Bergmann" <arnd@...nel.org>
To: "Bjorn Helgaas" <helgaas@...nel.org>, "Gerd Bayer" <gbayer@...ux.ibm.com>
Cc: "Hans Zhang" <18255117159@....com>, bhelgaas@...gle.com,
"Alexander Gordeev" <agordeev@...ux.ibm.com>,
"Christian Borntraeger" <borntraeger@...ux.ibm.com>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
jingoohan1@...il.com,
Krzysztof Wilczyński <kwilczynski@...nel.org>,
linux-kernel@...r.kernel.org, linux-s390@...r.kernel.org,
linux-next <linux-next@...r.kernel.org>, linux-pci@...r.kernel.org,
"Lorenzo Pieralisi" <lpieralisi@...nel.org>,
"Manivannan Sadhasivam" <mani@...nel.org>, "Rob Herring" <robh@...nel.org>,
"Niklas Schnelle" <schnelle@...ux.ibm.com>
Subject: Re: [PATCH] PCI: Fix endianness issues in pci_bus_read_config()
On Thu, Jul 31, 2025, at 20:39, Bjorn Helgaas wrote:
> On Thu, Jul 31, 2025 at 07:38:58PM +0200, Gerd Bayer wrote:
>>
>> - if (size == 1)
>> - return pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
>> - else if (size == 2)
>> - return pci_bus_read_config_word(bus, devfn, where, (u16 *)val);
>> - else if (size == 4)
>> - return pci_bus_read_config_dword(bus, devfn, where, val);
>> - else
>> - return PCIBIOS_BAD_REGISTER_NUMBER;
>> + if (size == 1) {
>> + rc = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
>> +#if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
>> + *val = ((*val >> 24) & 0xff);
>> +#endif
>
> Yeah, this is all pretty ugly. Obviously the previous code in
> __pci_find_next_cap_ttl() didn't need this. My guess is that was
> because the destination for the read data was always the correct type
> (u8/u16/u32), but here we always use a u32 and cast it to the
> appropriate type. Maybe we can use the correct types here instead of
> the casts?
Agreed, the casts here just add more potential for bugs.
The pci_bus_read_config() interface itself may have been a
mistake, can't the callers just use the underlying helpers
directly?
Arnd
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