linux-kernel - Re: [PATCH v4 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq

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Message-ID: <aIsnVuWnwBisCm82@hu-varada-blr.qualcomm.com>
Date: Thu, 31 Jul 2025 13:50:38 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
CC: <andersson@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>,
        <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
        <konradybcio@...nel.org>, <rafael@...nel.org>,
        <viresh.kumar@...aro.org>, <ilia.lin@...nel.org>, <djakov@...nel.org>,
        <quic_srichara@...cinc.com>, <quic_mdalam@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-pm@...r.kernel.org>
Subject: Re: [PATCH v4 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq

On Wed, Jul 30, 2025 at 02:49:58PM +0200, Konrad Dybcio wrote:
> On 7/30/25 10:13 AM, Varadarajan Narayanan wrote:
> > From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> >
> > Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for
> > CPU clock scaling.
> >
> > Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> > [ Added interconnect related entries, fix dt-bindings errors ]
> > Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> > ---
>
> [...]
>
> > +	cpu_opp_table: opp-table-cpu {
> > +		compatible = "operating-points-v2-kryo-cpu";
> > +		opp-shared;
> > +		nvmem-cells = <&cpu_speed_bin>;
> > +
> > +		opp-1416000000 {
>
> These rates seem quite high, are there no lower fstates for idling?

Will check on this and update.

> > +			opp-hz = /bits/ 64 <1416000000>;
> > +			opp-microvolt = <1>;
> > +			opp-supported-hw = <0x3>;
> > +			clock-latency-ns = <200000>;
> > +			opp-peak-kBps = <984000>;
> > +		};
> > +
> > +		opp-1800000000 {
> > +			opp-hz = /bits/ 64 <1800000000>;
> > +			opp-microvolt = <2>;
> > +			opp-supported-hw = <0x1>;
> > +			clock-latency-ns = <200000>;
> > +			opp-peak-kBps = <1272000>;
> > +		};
> > +	};
> > +
> >  	memory@...00000 {
> >  		device_type = "memory";
> >  		/* We expect the bootloader to fill in the size */
> > @@ -388,6 +428,18 @@ system-cache-controller@...000 {
> >  			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> >  		};
> >
> > +		qfprom@...00 {
> > +			compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
> > +			reg = <0x0 0x000a6000 0x0 0x1000>;
>
> The block is a bit bigger

Per the documentation, the block is 4KB. But the last register is at 0xa62bc.

> On IPQ platforms, can the OS blow fuses directly without TZ
> interference?

No.

> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +
> > +			cpu_speed_bin: cpu-speed-bin@234 {
> > +				reg = <0x234 0x1>;
> > +				bits = <0 8>;
> > +			};
> > +		};
> > +
> >  		tlmm: pinctrl@...0000 {
> >  			compatible = "qcom,ipq5424-tlmm";
> >  			reg = <0 0x01000000 0 0x300000>;
> > @@ -730,6 +782,15 @@ frame@...d000 {
> >  			};
> >  		};
> >
> > +		apss_clk: clock@...0000 {
> > +			compatible = "qcom,ipq5424-apss-clk";
> > +			reg = <0x0 0x0fa80000 0x0 0x20000>;
>
> Let's make it 0x30_000 to reserve the actual carved out reg space

ok.

> > +			clocks = <&xo_board>, <&gcc GPLL0>;
> > +			clock-names = "xo", "clk_ref";
>
> 1 per line would be perfect

Sure.

Thanks
Varada