Message-ID: <6d2cq657lkwrzntlwwyc5drgkh4vsetkppugrhjedpp7hlvdh5@lqwe34oyuuvb>
Date: Thu, 31 Jul 2025 12:00:33 +0200
From: Uwe Kleine-König <ukleinek@...nel.org>
To: Andre Przywara <andre.przywara@....com>
Cc: Alexandre Belloni <alexandre.belloni@...tlin.com>, 
	Aleksandr Shubin <privatesub2@...il.com>, linux-kernel@...r.kernel.org, 
	Conor Dooley <conor.dooley@...rochip.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>, 
	Jernej Skrabec <jernej.skrabec@...il.com>, Samuel Holland <samuel@...lland.org>, 
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, 
	Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, 
	Philipp Zabel <p.zabel@...gutronix.de>, Cheo Fusi <fusibrandon13@...il.com>, linux-pwm@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-sunxi@...ts.linux.dev, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v12 1/3] dt-bindings: pwm: Add binding for Allwinner
 D1/T113-S3/R329 PWM controller

Hello Andre,

On Thu, Jun 19, 2025 at 01:10:44PM +0100, Andre Przywara wrote:
> On Thu, 19 Jun 2025 11:44:07 +0200
> Alexandre Belloni <alexandre.belloni@...tlin.com> wrote:
> 
> Hi Alexandre,
> 
> > On 12/05/2025 23:56:19+0100, Andre Przywara wrote:
> > > On Sun, 27 Apr 2025 17:24:53 +0300
> > > Aleksandr Shubin <privatesub2@...il.com> wrote:
> > > 
> > > Hi,
> > >   
> > > > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm
> > > > controller witch is different from the previous pwm-sun4i.
> > > > 
> > > > The D1 and T113 are identical in terms of peripherals,
> > > > they differ only in the architecture of the CPU core, and
> > > > even share the majority of their DT. Because of that,
> > > > using the same compatible makes sense.
> > > > The R329 is a different SoC though, and should have
> > > > a different compatible string added, especially as there
> > > > is a difference in the number of channels.
> > > > 
> > > > D1 and T113s SoCs have one PWM controller with 8 channels.
> > > > R329 SoC has two PWM controllers in both power domains, one of
> > > > them has 9 channels (CPUX one) and the other has 6 (CPUS one).
> > > > 
> > > > Add a device tree binding for them.
> > > > 
> > > > Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> > > > Signed-off-by: Aleksandr Shubin <privatesub2@...il.com>
> > > > ---
> > > >  .../bindings/pwm/allwinner,sun20i-pwm.yaml    | 84 +++++++++++++++++++
> > > >  1 file changed, 84 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
> > > > new file mode 100644
> > > > index 000000000000..4b25e94a8e46
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
> > > > @@ -0,0 +1,84 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Allwinner D1, T113-S3 and R329 PWM
> > > > +
> > > > +maintainers:
> > > > +  - Aleksandr Shubin <privatesub2@...il.com>
> > > > +  - Brandon Cheo Fusi <fusibrandon13@...il.com>
> > > > +
> > > > +properties:
> > > > +  compatible:
> > > > +    oneOf:
> > > > +      - const: allwinner,sun20i-d1-pwm
> > > > +      - items:
> > > > +          - const: allwinner,sun50i-r329-pwm
> > > > +          - const: allwinner,sun20i-d1-pwm
> > > > +
> > > > +  reg:
> > > > +    maxItems: 1
> > > > +
> > > > +  "#pwm-cells":
> > > > +    const: 3
> > > > +
> > > > +  clocks:
> > > > +    items:
> > > > +      - description: Bus clock
> > > > +      - description: 24 MHz oscillator
> > > > +      - description: APB clock
> > > > +
> > > > +  clock-names:
> > > > +    items:
> > > > +      - const: bus
> > > > +      - const: hosc
> > > > +      - const: apb
> > > > +
> > > > +  resets:
> > > > +    maxItems: 1
> > > > +
> > > > +  allwinner,npwms:
> > > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > > +    description: The number of PWM channels configured for this instance
> > > > +    enum: [6, 8, 9]  
> > > 
> > > Do we really need to be so restrictive here? The IP has an
> > > "architectural" limit of 16 channels (due to the MMIO register layout
> > > and status/control bits usage in some registers), so can't we just leave
> > > this value to be anything between 1 and 16 here? If people configure
> > > this wrongly, it's their fault, I'd say? Without confining this further
> > > based on the respective compatible strings this enum is less useful
> > > anyway, I think. The Allwinner A523 uses the same IP, and supports all
> > > 16 channels, the V853 implements 12, that's what I quickly found
> > > already, and there might be more examples in the future, so I'd rather
> > > open this up.
> > >   
> > 
> > Do we really need this property? I feel like the number of PWM channels should be
> > something the driver could infer from the compatible string as we are going to
> > have one compatible string per SoC anyway.
> 
> Well yes, this would work, but I feel like it creates unnecessary churn to
> touch the driver every time some new SoC with the same IP pops up, and
> where just the number of channels is different - see above for a list of
> SoCs we already know about, and there are more in the pipe. It also means
> stable kernels would already work.

Having a property that specifies the number of PWM outputs is fine for
me.

There is some prior art for that: mxs-pwm.yaml has fsl,pwm-number;
pwm-st.txt has st,pwm-num-chan with that semantic.

Given that this is a fundamental concept of a pwm chip, I'd say giving
that a generic name without vendor prefix is justified. I suggest to go
for

	npwms = <..>;

which matches ngpios that is specified for gpio chips.

Best regards
Uwe

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