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Message-ID: <20250731140146.62960-8-daniel.lezcano@linaro.org>
Date: Thu, 31 Jul 2025 16:01:40 +0200
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: mbrugger@...e.com,
chester62515@...il.com,
ghennadi.procopciuc@....nxp.com,
shawnguo@...nel.org,
s.hauer@...gutronix.de
Cc: s32@....com,
kernel@...gutronix.de,
festevam@...il.com,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
linux-arm-kernel@...ts.infradead.org,
imx@...ts.linux.dev,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Ghennadi Procopciuc <ghennadi.procopciuc@....com>,
Thomas Fossati <thomas.fossati@...aro.org>
Subject: [PATCH v2 7/8] arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes
Referred in the documentation as the Software Timer Watchdog (SWT),
the s32g3 has 12 watchdogs. The number of watchdogs is designed to
allow dedicating one watchdog per Cortex-M7/A53 present on the SoC.
Add the SWT nodes in the device tree.
Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: Ghennadi Procopciuc <ghennadi.procopciuc@....com>
Cc: Thomas Fossati <thomas.fossati@...aro.org>
---
arch/arm64/boot/dts/freescale/s32g3.dtsi | 96 ++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index c2c986f03986..0ceb0807537a 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -374,6 +374,38 @@ usdhc0-200mhz-grp4 {
};
};
+ swt0: watchdog@...00000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40100000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt1: watchdog@...04000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40104000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt2: watchdog@...08000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40108000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt3: watchdog@...0c000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x4010c000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
stm0: timer@...1c000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x4011c000 0x3000>;
@@ -507,6 +539,38 @@ i2c2: i2c@...ec000 {
status = "disabled";
};
+ swt4: watchdog@...00000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40200000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt5: watchdog@...04000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40204000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt6: watchdog@...08000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40208000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt7: watchdog@...0C000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x4020C000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
stm4: timer@...1c000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x4021c000 0x3000>;
@@ -623,6 +687,38 @@ usdhc0: mmc@...f0000 {
status = "disabled";
};
+ swt8: watchdog@...00000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <40500000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt9: watchdog@...04000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40504000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt10: watchdog@...08000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x40508000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
+ swt11: watchdog@...0c000 {
+ compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
+ reg = <0x4050c000 0x1000>;
+ clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
+ clock-names = "counter", "module", "register";
+ status = "disabled";
+ };
+
stm8: timer@...20000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40520000 0x3000>;
--
2.43.0
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