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Message-ID: <aIwzrHKD-GiZ0oFv@ketchup>
Date: Fri, 1 Aug 2025 03:25:32 +0000
From: Haylen Chu <heylenay@....org>
To: Troy Mitchell <troy.mitchell@...ux.spacemit.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Yixun Lan <dlan@...too.org>,
Alex Elder <elder@...cstar.com>,
Inochi Amaoto <inochiama@...look.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-riscv@...ts.infradead.org,
spacemit@...ts.linux.dev, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Yao Zi <ziyao@...root.org>
Subject: Re: [PATCH RESEND v3 2/2] clk: spacemit: fix sspax_clk
On Thu, Jul 31, 2025 at 10:14:07PM +0800, Troy Mitchell wrote:
> Hardware Requirement:
> When FNCLKSEL in APBC_SSPAX_CLK_RST is set to 7 (3'b111),
> BIT3 must be set to 1 for the SSPAx parent clock to be I2S_BCLK.
The change itself looks good to me. But additionally, maybe it's helpful
to have a comment explaining this, just like twsi8_clk's case.
> This patch introduces SSPAx_I2S_BCLK as a virtual gate to enable BIT3.
>
> Signed-off-by: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
> Suggested-by: Yao Zi <ziyao@...root.org>
> ---
> drivers/clk/spacemit/ccu-k1.c | 25 +++++++++++++++++++++----
> 1 file changed, 21 insertions(+), 4 deletions(-)
With a comment added, feel free to add my
Reviewed-by: Haylen Chu <heylenay@....org>
Regards,
Haylen Chu
> diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
> index cdde37a0523537c2f436e481ae8d6ec5a581b87e..24a561499a7c11b6a661c026f0bd2fac28fe7b04 100644
> --- a/drivers/clk/spacemit/ccu-k1.c
> +++ b/drivers/clk/spacemit/ccu-k1.c
> @@ -349,7 +349,10 @@ CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1),
>
> CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);
>
> -static const struct clk_parent_data sspa_parents[] = {
> +CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0);
> +CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0);
> +
> +static const struct clk_parent_data sspa0_parents[] = {
> CCU_PARENT_HW(pll1_d384_6p4),
> CCU_PARENT_HW(pll1_d192_12p8),
> CCU_PARENT_HW(pll1_d96_25p6),
> @@ -357,10 +360,22 @@ static const struct clk_parent_data sspa_parents[] = {
> CCU_PARENT_HW(pll1_d768_3p2),
> CCU_PARENT_HW(pll1_d1536_1p6),
> CCU_PARENT_HW(pll1_d3072_0p8),
> - CCU_PARENT_HW(i2s_bclk),
> + CCU_PARENT_HW(sspa0_i2s_bclk),
> };
> -CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
> -CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
> +CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
> +
> +static const struct clk_parent_data sspa1_parents[] = {
> + CCU_PARENT_HW(pll1_d384_6p4),
> + CCU_PARENT_HW(pll1_d192_12p8),
> + CCU_PARENT_HW(pll1_d96_25p6),
> + CCU_PARENT_HW(pll1_d48_51p2),
> + CCU_PARENT_HW(pll1_d768_3p2),
> + CCU_PARENT_HW(pll1_d1536_1p6),
> + CCU_PARENT_HW(pll1_d3072_0p8),
> + CCU_PARENT_HW(sspa1_i2s_bclk),
> +};
> +CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
> +
> CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0);
> CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0);
> CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0);
> @@ -965,6 +980,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] = {
> [CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw,
> [CLK_TSEN_BUS] = &tsen_bus_clk.common.hw,
> [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw,
> + [CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw,
> + [CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw,
> };
>
> static const struct spacemit_ccu_data k1_ccu_apbc_data = {
>
> --
> 2.50.0
>
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