| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <aIx1hGvud9n35Hx/@rli9-mobl>
Date: Fri, 1 Aug 2025 16:06:28 +0800
From: kernel test robot <lkp@...el.com>
To: Masahiro Yamada <masahiroy@...nel.org>
CC: <oe-kbuild-all@...ts.linux.dev>, <linux-kernel@...r.kernel.org>, "Max
Filippov" <jcmvbkbc@...il.com>
Subject: arch/xtensa/boot/dts/virt.dts:48.6-71.4: Warning
(unit_address_vs_reg): /pci: node has a reg or ranges property, but no unit
name
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: f2d282e1dfb3d8cb95b5ccdea43f2411f27201db
commit: 47812144d39566da3f1dbc7a615f656969f99337 xtensa: migrate to the generic rule for built-in DTB
date: 5 months ago
:::::: branch date: 4 hours ago
:::::: commit date: 5 months ago
config: xtensa-virt_defconfig (https://download.01.org/0day-ci/archive/20250801/202508010555.VHB3uhTJ-lkp@intel.com/config)
compiler: xtensa-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250801/202508010555.VHB3uhTJ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/r/202508010555.VHB3uhTJ-lkp@intel.com/
dtcheck warnings: (new ones prefixed by >>)
>> arch/xtensa/boot/dts/virt.dts:48.6-71.4: Warning (unit_address_vs_reg): /pci: node has a reg or ranges property, but no unit name
vim +48 arch/xtensa/boot/dts/virt.dts
775f1f7eacede5 Max Filippov 2018-11-05 3
775f1f7eacede5 Max Filippov 2018-11-05 4 / {
775f1f7eacede5 Max Filippov 2018-11-05 5 compatible = "cdns,xtensa-iss";
775f1f7eacede5 Max Filippov 2018-11-05 6 #address-cells = <1>;
775f1f7eacede5 Max Filippov 2018-11-05 7 #size-cells = <1>;
775f1f7eacede5 Max Filippov 2018-11-05 8 interrupt-parent = <&pic>;
775f1f7eacede5 Max Filippov 2018-11-05 9
775f1f7eacede5 Max Filippov 2018-11-05 10 chosen {
775f1f7eacede5 Max Filippov 2018-11-05 11 bootargs = "console=ttyS0,115200n8 debug";
775f1f7eacede5 Max Filippov 2018-11-05 12 };
775f1f7eacede5 Max Filippov 2018-11-05 13
775f1f7eacede5 Max Filippov 2018-11-05 14 memory@0 {
775f1f7eacede5 Max Filippov 2018-11-05 15 device_type = "memory";
775f1f7eacede5 Max Filippov 2018-11-05 16 reg = <0x00000000 0x80000000>;
775f1f7eacede5 Max Filippov 2018-11-05 17 };
775f1f7eacede5 Max Filippov 2018-11-05 18
775f1f7eacede5 Max Filippov 2018-11-05 19 cpus {
775f1f7eacede5 Max Filippov 2018-11-05 20 #address-cells = <1>;
775f1f7eacede5 Max Filippov 2018-11-05 21 #size-cells = <0>;
775f1f7eacede5 Max Filippov 2018-11-05 22 cpu@0 {
775f1f7eacede5 Max Filippov 2018-11-05 23 compatible = "cdns,xtensa-cpu";
775f1f7eacede5 Max Filippov 2018-11-05 24 reg = <0>;
775f1f7eacede5 Max Filippov 2018-11-05 25 clocks = <&osc>;
775f1f7eacede5 Max Filippov 2018-11-05 26 };
775f1f7eacede5 Max Filippov 2018-11-05 27 };
775f1f7eacede5 Max Filippov 2018-11-05 28
775f1f7eacede5 Max Filippov 2018-11-05 29 clocks {
775f1f7eacede5 Max Filippov 2018-11-05 30 osc: osc {
775f1f7eacede5 Max Filippov 2018-11-05 31 #clock-cells = <0>;
775f1f7eacede5 Max Filippov 2018-11-05 32 compatible = "fixed-clock";
775f1f7eacede5 Max Filippov 2018-11-05 33 clock-frequency = <40000000>;
775f1f7eacede5 Max Filippov 2018-11-05 34 };
775f1f7eacede5 Max Filippov 2018-11-05 35 };
775f1f7eacede5 Max Filippov 2018-11-05 36
775f1f7eacede5 Max Filippov 2018-11-05 37 pic: pic {
775f1f7eacede5 Max Filippov 2018-11-05 38 compatible = "cdns,xtensa-pic";
775f1f7eacede5 Max Filippov 2018-11-05 39 /* one cell: internal irq number,
775f1f7eacede5 Max Filippov 2018-11-05 40 * two cells: second cell == 0: internal irq number
775f1f7eacede5 Max Filippov 2018-11-05 41 * second cell == 1: external irq number
775f1f7eacede5 Max Filippov 2018-11-05 42 */
775f1f7eacede5 Max Filippov 2018-11-05 43 #address-cells = <0>;
775f1f7eacede5 Max Filippov 2018-11-05 44 #interrupt-cells = <2>;
775f1f7eacede5 Max Filippov 2018-11-05 45 interrupt-controller;
775f1f7eacede5 Max Filippov 2018-11-05 46 };
775f1f7eacede5 Max Filippov 2018-11-05 47
775f1f7eacede5 Max Filippov 2018-11-05 @48 pci {
:::::: The code at line 48 was first introduced by commit
:::::: 775f1f7eacede583ec25ed56e58c4483f2b29265 xtensa: virt: add defconfig and DTS
:::::: TO: Max Filippov <jcmvbkbc@...il.com>
:::::: CC: Max Filippov <jcmvbkbc@...il.com>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Powered by blists - more mailing lists