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Message-ID: <04687e3a-5761-4d1c-bece-fcc2241f0c28@oss.qualcomm.com>
Date: Mon, 4 Aug 2025 10:57:34 +0530
From: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
To: Imran Shaik <quic_imrashai@...cinc.com>,
Georgi Djakov
<djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Sibi Sankar
<quic_sibis@...cinc.com>,
Odelu Kukatla <quic_okukatla@...cinc.com>,
Mike Tipton <mike.tipton@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: qcs615: Add OSM l3 interconnect
provider node and CPU OPP tables to scale DDR/L3
On 8/4/2025 10:56 AM, Imran Shaik wrote:
>
>
> On 8/4/2025 10:35 AM, Raviteja Laggyshetty wrote:
>> Add Operation State Manager (OSM) L3 interconnect provide node and OPP
>> tables required to scale DDR and L3 per freq-domain on QCS615 SoC.
>> As QCS615 and SM8150 SoCs have same OSM hardware, added SM8150
>> compatible as fallback for QCS615 OSM device node.
>>
>> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
>> Signed-off-by: Imran Shaik <quic_imrashai@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm6150.dtsi | 148 +++++++++++++++++++++++++++
>> 1 file changed, 148 insertions(+)
>>
>
> This patch is functionally depends on cpufreq-w node change [1].
>
> [1] https://lore.kernel.org/all/20250702-qcs615-mm-cpu-dt-v4-v5-3-df24896cbb26@quicinc.com/
>
> Raviteja, As discussed, please mark the dependency on this change.
Sure, I will add dependency and post V2.
Thanks,
Raviteja
>
> Thanks,
> Imran
T
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