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Message-ID: <20250804061536.110-1-raviteja.laggyshetty@oss.qualcomm.com>
Date: Mon, 4 Aug 2025 06:15:34 +0000
From: Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
To: Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Sibi Sankar <quic_sibis@...cinc.com>,
Odelu Kukatla <quic_okukatla@...cinc.com>,
Mike Tipton <mike.tipton@....qualcomm.com>,
Imran Shaik <quic_imrashai@...cinc.com>
Cc: linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Raviteja Laggyshetty <raviteja.laggyshetty@....qualcomm.com>
Subject: [PATCH V2 0/2] Add OSM L3 provider support on QCS615 SoC
Add Operation State Manager (OSM) L3 scaling support on QCS615 SoC.
This series has functional dependency on [1].
[1] https://lore.kernel.org/all/20250702-qcs615-mm-cpu-dt-v4-v5-3-df24896cbb26@quicinc.com/
Changes since v1:
- Updated dependency on cpufreq patch [Imran].
- Updated SoB sequence [Dmitry].
- Link to v1: https://lore.kernel.org/all/20250804050542.100806-1-raviteja.laggyshetty@oss.qualcomm.com/
Raviteja Laggyshetty (2):
dt-bindings: interconnect: Add OSM L3 compatible for QCS615 SoC
arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and
CPU OPP tables to scale DDR/L3
.../bindings/interconnect/qcom,osm-l3.yaml | 5 +
arch/arm64/boot/dts/qcom/sm6150.dtsi | 148 ++++++++++++++++++
2 files changed, 153 insertions(+)
--
2.43.0
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