lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAHp75VcxZXk7N3F4f=edSTHXQO9reF2kvF3JUNxNu_J6VOuoRA@mail.gmail.com>
Date: Mon, 4 Aug 2025 10:57:57 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Hans de Goede <hansg@...nel.org>
Cc: Lee Jones <lee@...nel.org>, Andy Shevchenko <andy@...nel.org>, linux-kernel@...r.kernel.org, 
	stable@...r.kernel.org
Subject: Re: [PATCH] mfd: intel_soc_pmic_chtdc_ti: Set use_single_read
 regmap_config flag

On Mon, Aug 4, 2025 at 10:51 AM Hans de Goede <hansg@...nel.org> wrote:
> On 4-Aug-25 10:47 AM, Andy Shevchenko wrote:
> > On Mon, Aug 4, 2025 at 10:34 AM Hans de Goede <hansg@...nel.org> wrote:

...

> >> +       /* Reading multiple registers at once is not supported */
> >> +       .use_single_read = true,
> >
> > By HW or by problem in regmap as being suggested here:
> > https://lore.kernel.org/linux-gpio/CALNFmy1ZRqHz6_DD_2qamm-iLQ51AOFQH=ahCWRN7SAk3pfZ_A@mail.gmail.com/
> > ?
>
> This is a hw limitation. I tried with i2ctransfer to directly
> access the chip and it returns invalid values (1) after
> the first byte read.

> 1) I don't remember if it was 0, 0xff or repeating
> of the first byte. But it definitely did not work.

Perhaps elaborate the above in the comment, by at least putting
keyword HW there?

-- 
With Best Regards,
Andy Shevchenko

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ