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Message-ID: <CAMuHMdW0CTM+d-N0FgP=dKoSTdmRr2Rpg2Rtzj33gDk8qW+FUw@mail.gmail.com>
Date: Mon, 4 Aug 2025 11:28:13 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: John Madieu <john.madieu.xa@...renesas.com>
Cc: conor+dt@...nel.org, daniel.lezcano@...aro.org, krzk+dt@...nel.org,
rafael@...nel.org, biju.das.jz@...renesas.com, devicetree@...r.kernel.org,
john.madieu@...il.com, linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, lukasz.luba@....com, magnus.damm@...il.com,
robh@...nel.org, rui.zhang@...el.com, sboyd@...nel.org,
niklas.soderlund+renesas@...natech.se
Subject: Re: [PATCH v6 3/5] thermal: renesas: rzg3e: Add thermal driver for
the Renesas RZ/G3E SoC
Hi John,
On Thu, 22 May 2025 at 20:23, John Madieu <john.madieu.xa@...renesas.com> wrote:
> The RZ/G3E SoC integrates a Temperature Sensor Unit (TSU) block designed
> to monitor the chip's junction temperature. This sensor is connected to
> channel 1 of the APB port clock/reset and provides temperature measurements.
>
> It also requires calibration values stored in the system controller registers
> for accurate temperature measurement. Add a driver for the Renesas RZ/G3E TSU.
>
> Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
Thanks for your patch!
The TSUs in RZ/V2H and RZ/V2N seem to be identical to the one in RZ/G3E.
However, RZ/V2H and RZ/V2N have two instances, while RZ/G3 has only one.
> --- /dev/null
> +++ b/drivers/thermal/renesas/rzg3e_thermal.c
> @@ -0,0 +1,443 @@
> +/* SYS Trimming register offsets macro */
> +#define SYS_TSU_TRMVAL(x) (0x330 + (x) * 4)
RZ/V2H and RZ/V2N have a second set of trim values for the second
TSU instance. So I guess you want to specify the offset in DT instead.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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