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Message-ID: <13467efc-7c79-4d06-af1c-301b852a530c@altera.com>
Date: Mon, 4 Aug 2025 07:57:55 -0700
From: Matthew Gerlach <matthew.gerlach@...era.com>
To: andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, mcoquelin.stm32@...il.com,
alexandre.torgue@...s.st.com, dinguyen@...nel.org,
maxime.chevallier@...tlin.com, richardcochran@...il.com,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: Mun Yew Tham <mun.yew.tham@...era.com>
Subject: Re: [PATCH v2 2/4] arm64: dts: Agilex5 Add gmac nodes to DTSI for
Agilex5
On 7/24/25 8:40 AM, Matthew Gerlach wrote:
> From: Mun Yew Tham <mun.yew.tham@...era.com>
>
> Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI
> for the Agilex5 SOCFPGA. Agilex5 has three Ethernet controllers based on
> Synopsys DWC XGMAC IP version 2.10.
>
> Signed-off-by: Mun Yew Tham <mun.yew.tham@...era.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...era.com>
> ---
> v2:
> - Remove generic compatible string for Agilex5.
> ---
> .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++
> 1 file changed, 336 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 7d9394a04302..04e99cd7e74b 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -486,5 +486,341 @@ qspi: spi@...d2000 {
> clocks = <&qspi_clk>;
> status = "disabled";
> };
Is there any feedback for this patch and the next one in the series,
"[PATCH v2 3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the
Agilex5 dev kit"?
Thanks,
Matthew Gerlach
> +
> + gmac0: ethernet@...10000 {
> + compatible = "altr,socfpga-stmmac-agilex5",
> + "snps,dwxgmac-2.10";
> + reg = <0x10810000 0x3500>;
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
> + reset-names = "stmmaceth", "ahb";
> + clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
> + <&clkmgr AGILEX5_EMAC_PTP_CLK>;
> + clock-names = "stmmaceth", "ptp_ref";
> + mac-address = [00 00 00 00 00 00];
> + tx-fifo-depth = <32768>;
> + rx-fifo-depth = <16384>;
> + snps,multicast-filter-bins = <64>;
> + snps,perfect-filter-entries = <64>;
> + snps,axi-config = <&stmmac_axi_emac0_setup>;
> + snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
> + snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
> + snps,pbl = <32>;
> + snps,tso;
> + altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> + snps,clk-csr = <0>;
> + status = "disabled";
> +
> + stmmac_axi_emac0_setup: stmmac-axi-config {
> + snps,wr_osr_lmt = <31>;
> + snps,rd_osr_lmt = <31>;
> + snps,blen = <0 0 0 32 16 8 4>;
> + };
> +
> + mtl_rx_emac0_setup: rx-queues-config {
> + snps,rx-queues-to-use = <8>;
> + snps,rx-sched-sp;
> + queue0 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x0>;
> + };
> + queue1 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x1>;
> + };
> + queue2 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x2>;
> + };
> + queue3 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x3>;
> + };
> + queue4 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x4>;
> + };
> + queue5 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x5>;
> + };
> + queue6 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x6>;
> + };
> + queue7 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x7>;
> + };
> + };
> +
> + mtl_tx_emac0_setup: tx-queues-config {
> + snps,tx-queues-to-use = <8>;
> + snps,tx-sched-wrr;
> + queue0 {
> + snps,weight = <0x09>;
> + snps,dcb-algorithm;
> + };
> + queue1 {
> + snps,weight = <0x0A>;
> + snps,dcb-algorithm;
> + };
> + queue2 {
> + snps,weight = <0x0B>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue3 {
> + snps,weight = <0x0C>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue4 {
> + snps,weight = <0x0D>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue5 {
> + snps,weight = <0x0E>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue6 {
> + snps,weight = <0x0F>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue7 {
> + snps,weight = <0x10>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + };
> + };
> +
> + gmac1: ethernet@...20000 {
> + compatible = "altr,socfpga-stmmac-agilex5",
> + "snps,dwxgmac-2.10";
> + reg = <0x10820000 0x3500>;
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
> + reset-names = "stmmaceth", "ahb";
> + clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
> + <&clkmgr AGILEX5_EMAC_PTP_CLK>;
> + clock-names = "stmmaceth", "ptp_ref";
> + mac-address = [00 00 00 00 00 00];
> + tx-fifo-depth = <32768>;
> + rx-fifo-depth = <16384>;
> + snps,multicast-filter-bins = <64>;
> + snps,perfect-filter-entries = <64>;
> + snps,axi-config = <&stmmac_axi_emac1_setup>;
> + snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
> + snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
> + snps,pbl = <32>;
> + snps,tso;
> + altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> + snps,clk-csr = <0>;
> + status = "disabled";
> +
> + stmmac_axi_emac1_setup: stmmac-axi-config {
> + snps,wr_osr_lmt = <31>;
> + snps,rd_osr_lmt = <31>;
> + snps,blen = <0 0 0 32 16 8 4>;
> + };
> +
> + mtl_rx_emac1_setup: rx-queues-config {
> + snps,rx-queues-to-use = <8>;
> + snps,rx-sched-sp;
> + queue0 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x0>;
> + };
> + queue1 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x1>;
> + };
> + queue2 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x2>;
> + };
> + queue3 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x3>;
> + };
> + queue4 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x4>;
> + };
> + queue5 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x5>;
> + };
> + queue6 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x6>;
> + };
> + queue7 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x7>;
> + };
> + };
> +
> + mtl_tx_emac1_setup: tx-queues-config {
> + snps,tx-queues-to-use = <8>;
> + snps,tx-sched-wrr;
> + queue0 {
> + snps,weight = <0x09>;
> + snps,dcb-algorithm;
> + };
> + queue1 {
> + snps,weight = <0x0A>;
> + snps,dcb-algorithm;
> + };
> + queue2 {
> + snps,weight = <0x0B>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue3 {
> + snps,weight = <0x0C>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue4 {
> + snps,weight = <0x0D>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue5 {
> + snps,weight = <0x0E>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue6 {
> + snps,weight = <0x0F>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue7 {
> + snps,weight = <0x10>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + };
> + };
> +
> + gmac2: ethernet@...30000 {
> + compatible = "altr,socfpga-stmmac-agilex5",
> + "snps,dwxgmac-2.10";
> + reg = <0x10830000 0x3500>;
> + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
> + reset-names = "stmmaceth", "ahb";
> + clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
> + <&clkmgr AGILEX5_EMAC_PTP_CLK>;
> + clock-names = "stmmaceth", "ptp_ref";
> + mac-address = [00 00 00 00 00 00];
> + tx-fifo-depth = <32768>;
> + rx-fifo-depth = <16384>;
> + snps,multicast-filter-bins = <64>;
> + snps,perfect-filter-entries = <64>;
> + snps,axi-config = <&stmmac_axi_emac2_setup>;
> + snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
> + snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
> + snps,pbl = <32>;
> + snps,tso;
> + altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
> + snps,clk-csr = <0>;
> + status = "disabled";
> +
> + stmmac_axi_emac2_setup: stmmac-axi-config {
> + snps,wr_osr_lmt = <31>;
> + snps,rd_osr_lmt = <31>;
> + snps,blen = <0 0 0 32 16 8 4>;
> + };
> +
> + mtl_rx_emac2_setup: rx-queues-config {
> + snps,rx-queues-to-use = <8>;
> + snps,rx-sched-sp;
> + queue0 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x0>;
> + };
> + queue1 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x1>;
> + };
> + queue2 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x2>;
> + };
> + queue3 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x3>;
> + };
> + queue4 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x4>;
> + };
> + queue5 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x5>;
> + };
> + queue6 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x6>;
> + };
> + queue7 {
> + snps,dcb-algorithm;
> + snps,map-to-dma-channel = <0x7>;
> + };
> + };
> +
> + mtl_tx_emac2_setup: tx-queues-config {
> + snps,tx-queues-to-use = <8>;
> + snps,tx-sched-wrr;
> + queue0 {
> + snps,weight = <0x09>;
> + snps,dcb-algorithm;
> + };
> + queue1 {
> + snps,weight = <0x0A>;
> + snps,dcb-algorithm;
> + };
> + queue2 {
> + snps,weight = <0x0B>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue3 {
> + snps,weight = <0x0C>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue4 {
> + snps,weight = <0x0D>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue5 {
> + snps,weight = <0x0E>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue6 {
> + snps,weight = <0x0F>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + queue7 {
> + snps,weight = <0x10>;
> + snps,coe-unsupported;
> + snps,dcb-algorithm;
> + };
> + };
> + };
> };
> };
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