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Message-Id: <1754358421-12578-2-git-send-email-nobuhiro1.iwamatsu@toshiba.co.jp>
Date: Tue, 5 Aug 2025 10:47:00 +0900
From: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
To: Frank.Li@....com, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
bhelgaas@...gle.com
Cc: linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
yuji2.ishikawa@...hiba.co.jp,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
Subject: [PATCH v2 1/2] arm64: dts: toshiba: Update SoC and PCIe ranges to reflect hardware behavior
From: Frank Li <Frank.Li@....com>
tmpv7708 trim address bit[31:30] in tmpv7708 before passing to the PCIe
controller. Since only PCIe controller needs to convert the address range
0x40000000 - 0x80000000, add a bus definition, describe the ranges in it,
and move the PCIe definition.
Prepare for the removal of the driver’s cpu_addr_fixup().
Signed-off-by: Frank Li <Frank.Li@....com>
Suggested-by: Yuji Ishikawa <yuji2.ishikawa@...hiba.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>
---
v2:
Update commit message.
Fix range.
Set true to use_parent_dt_ranges in pcie-visconti.c.
move pcie under the dedicated sub-bus.
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 75 +++++++++++++---------
drivers/pci/controller/dwc/pcie-visconti.c | 2 +
2 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
index 39806f0ae5133..b754965a76ca6 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
@@ -478,37 +478,52 @@ pwm: pwm@...c0000 {
status = "disabled";
};
- pcie: pcie@...00000 {
- compatible = "toshiba,visconti-pcie";
- reg = <0x0 0x28400000 0x0 0x00400000>,
- <0x0 0x70000000 0x0 0x10000000>,
- <0x0 0x28050000 0x0 0x00010000>,
- <0x0 0x24200000 0x0 0x00002000>,
- <0x0 0x24162000 0x0 0x00001000>;
- reg-names = "dbi", "config", "ulreg", "smu", "mpu";
- device_type = "pci";
- bus-range = <0x00 0xff>;
- num-lanes = <2>;
- num-viewport = <8>;
-
- #address-cells = <3>;
+ pcie_bus: bus@...00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
#size-cells = <2>;
- #interrupt-cells = <1>;
- ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
- 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi", "intr";
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map =
- <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
- 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
- max-link-speed = <2>;
- clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
- clock-names = "ref", "core", "aux";
- status = "disabled";
+ ranges = /* register 1:1 map */
+ <0x0 0x24000000 0x0 0x24000000 0x0 0x0C000000>,
+ /*
+ * bus fabric mask address bit 30 and 31 to 0
+ * before send to PCIe controller.
+ *
+ * PCIe map address 0 to cpu's 0x40000000
+ */
+ <0x0 0x00000000 0x0 0x40000000 0x0 0x40000000>;
+
+ pcie: pcie@...00000 {
+ compatible = "toshiba,visconti-pcie";
+ reg = <0x0 0x28400000 0x0 0x00400000>,
+ <0x0 0x30000000 0x0 0x10000000>,
+ <0x0 0x28050000 0x0 0x00010000>,
+ <0x0 0x24200000 0x0 0x00002000>,
+ <0x0 0x24162000 0x0 0x00001000>;
+ reg-names = "dbi", "config", "ulreg", "smu", "mpu";
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ num-viewport = <8>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x81000000 0 0x00000000 0 0x00000000 0 0x00010000
+ 0x82000000 0 0x10000000 0 0x10000000 0 0x20000000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "intr";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map =
+ <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ max-link-speed = <2>;
+ clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>;
+ clock-names = "ref", "core", "aux";
+ status = "disabled";
+ };
};
};
};
diff --git a/drivers/pci/controller/dwc/pcie-visconti.c b/drivers/pci/controller/dwc/pcie-visconti.c
index cdeac6177143c..2a724ab587f78 100644
--- a/drivers/pci/controller/dwc/pcie-visconti.c
+++ b/drivers/pci/controller/dwc/pcie-visconti.c
@@ -310,6 +310,8 @@ static int visconti_pcie_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pcie);
+ pci->use_parent_dt_ranges = true;
+
return visconti_add_pcie_port(pcie, pdev);
}
--
2.49.0
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