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Message-ID: <4jvbnswz2445k67hy7xo4t62zevelk4bond2bzgjnsuzf57ah2@mmif5he65o6k>
Date: Tue, 5 Aug 2025 08:16:27 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Varadarajan Narayanan <quic_varada@...cinc.com>
Cc: andersson@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
konradybcio@...nel.org, rafael@...nel.org, viresh.kumar@...aro.org,
ilia.lin@...nel.org, djakov@...nel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
Sricharan Ramabadhran <quic_srichara@...cinc.com>,
Md Sadre Alam <quic_mdalam@...cinc.com>
Subject: Re: [PATCH v5 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424
apss clock controller
On Mon, Aug 04, 2025 at 04:50:38PM +0530, Varadarajan Narayanan wrote:
> From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>
> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> The RCG and PLL have a separate register space from the GCC.
> Also the L3 cache has a separate pll and needs to be scaled along
> with the CPU.
>
> Co-developed-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> [ Added interconnect related changes ]
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> ---
> v5: Remove previous maintainers
> Change clock@...0000 to clock-controller@...0000 in example
> Have one item per line for clocks and clock-names in example
>
> v4: Add self to 'maintainers'
> s/gpll0/clk_ref/ in clock-names
> s/apss-clock/clock/ in example's node name
>
> v2: Add #interconnect-cells to help enable L3 pll as ICC clock
> Add master/slave ids
> ---
> .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 63 +++++++++++++++++++
> include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++
> .../dt-bindings/interconnect/qcom,ipq5424.h | 3 +
> 3 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
> new file mode 100644
> index 000000000000..0154016075de
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm APSS IPQ5424 Clock Controller
> +
> +maintainers:
> + - Varadarajan Narayanan <quic_varada@...cinc.com>
> +
> +description:
> + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> + The RCG and PLL have a separate register space from the GCC.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq5424-apss-clk
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Reference to the XO clock.
> + - description: Reference to the GPLL0 clock.
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: clk_ref
You should not need clock-names now, please use indices.
> +
> + '#clock-cells':
> + const: 1
> +
> + '#interconnect-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#interconnect-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
> +
> + apss_clk: clock-controller@...0000 {
> + compatible = "qcom,ipq5424-apss-clk";
> + reg = <0x0fa80000 0x20000>;
> + clocks = <&xo_board>,
> + <&gcc GPLL0>;
> + clock-names = "xo",
> + "clk_ref";
> + #clock-cells = <1>;
> + #interconnect-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
> index 77b6e05492e2..0bb41e5efdef 100644
> --- a/include/dt-bindings/clock/qcom,apss-ipq.h
> +++ b/include/dt-bindings/clock/qcom,apss-ipq.h
> @@ -8,5 +8,11 @@
>
> #define APCS_ALIAS0_CLK_SRC 0
> #define APCS_ALIAS0_CORE_CLK 1
> +#define APSS_PLL_EARLY 2
> +#define APSS_SILVER_CLK_SRC 3
> +#define APSS_SILVER_CORE_CLK 4
> +#define L3_PLL 5
> +#define L3_CLK_SRC 6
> +#define L3_CORE_CLK 7
>
> #endif
> diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h
> index a770356112ee..afd7e0683a24 100644
> --- a/include/dt-bindings/interconnect/qcom,ipq5424.h
> +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h
> @@ -21,4 +21,7 @@
> #define MASTER_CNOC_USB 16
> #define SLAVE_CNOC_USB 17
>
> +#define MASTER_CPU 0
> +#define SLAVE_L3 1
> +
> #endif /* INTERCONNECT_QCOM_IPQ5424_H */
> --
> 2.34.1
>
--
With best wishes
Dmitry
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