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Message-ID: <20250805090021.1407753-1-w.egorov@phytec.de>
Date: Tue, 5 Aug 2025 11:00:20 +0200
From: Wadim Egorov <w.egorov@...tec.de>
To: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>
CC: <linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <upstream@...ts.phytec.de>
Subject: [PATCH] arm64: dts: ti: k3-am62a-phycore-som: Add 1.4GHz opp entry
The phyCORE-AM62Ax is capable of supplying 0v85 to the VDD_CORE
which allows the Cortex-A53s to operate at 1.4GHz according to chapter
7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table
to enable this OPP
[0] https://www.ti.com/lit/ds/symlink/am62a3.pdf
Signed-off-by: Wadim Egorov <w.egorov@...tec.de>
---
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
index 5dc5d2cb20cc..207ca00630d1 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
@@ -200,6 +200,15 @@ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
};
};
+&a53_opp_table {
+ /* Requires VDD_CORE at 0v85 */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ };
+};
+
&c7x_0 {
mboxes = <&mailbox0_cluster1 &mbox_c7x_0>;
memory-region = <&c7x_0_dma_memory_region>,
--
2.48.1
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