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Message-ID: <7e4d9dfe-428f-4374-9be7-97123cf36e5a@oss.qualcomm.com>
Date: Tue, 5 Aug 2025 20:24:07 +0800
From: Fange Zhang <fange.zhang@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Xiangxu Yin <xiangxu.yin@....qualcomm.com>,
Li Liu <quic_lliu6@...cinc.com>, Dmitry Baryshkov <lumag@...nel.org>
Subject: Re: [PATCH v5 1/2] arm64: dts: qcom: Add display support for QCS615
On 7/29/2025 7:17 PM, Konrad Dybcio wrote:
> On 7/18/25 2:56 PM, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@...cinc.com>
>>
>> Add display MDSS and DSI configuration for QCS615 platform.
>> QCS615 has a DP port, and DP support will be added in a later patch.
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>> Signed-off-by: Li Liu <quic_lliu6@...cinc.com>
>> Signed-off-by: Fange Zhang <fange.zhang@....qualcomm.com>
>> ---
>
> [...]
>
>> +
>> + mdss_mdp: display-controller@...1000 {
>> + compatible = "qcom,sm6150-dpu";
>> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
>> + <0x0 0x0aeb0000 0x0 0x2008>;
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "iface", "bus", "core", "vsync";
>
> 1 per line please, everywhere> +
Got it will fix it in next patch>> + assigned-clocks = <&dispcc
DISP_CC_MDSS_VSYNC_CLK>;
>> + assigned-clock-rates = <19200000>;
>
> Is this necessary?
test pass without this, so will remove them in next patch>
>> +
>> + operating-points-v2 = <&mdp_opp_table>;
>> + power-domains = <&rpmhpd RPMHPD_CX>;
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <0>;
>
> interrupts-extended
Got it, will change it as below in next patch
interrupts-extended = <&mdss 0>;>
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>
> Please keep a \n between properties and subnodes
will fix it in next patch>
>> + dpu_intf0_out: endpoint {
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint = <&mdss_dsi0_in>;
>> + };
>> + };
>> + };
>> +
>> + mdp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-19200000 {
>> + opp-hz = /bits/ 64 <19200000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-25600000 {
>> + opp-hz = /bits/ 64 <25600000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>
> This and the above frequency are missing one zero (i.e. you
> have a 10x underclock)
Got it, will fix it in next patch>
> [...]
>
>> + mdss_dsi0_phy: phy@...4400 {
>> + compatible = "qcom,sm6150-dsi-phy-14nm";
>> + reg = <0x0 0x0ae94400 0x0 0x100>,
>> + <0x0 0x0ae94500 0x0 0x300>,
>> + <0x0 0x0ae94800 0x0 0x188>;
>
> sz = 0x124
Got it, will change 0x188 to 0x124 in next patch>
>> + reg-names = "dsi_phy",
>> + "dsi_phy_lane",
>> + "dsi_pll";
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "iface", "ref";
>> +
>> + status = "disabled";
>> + };
>> + };
>> +
>> dispcc: clock-controller@...0000 {
>> compatible = "qcom,qcs615-dispcc";
>> reg = <0 0x0af00000 0 0x20000>;
>>
>> clocks = <&rpmhcc RPMH_CXO_CLK>,
>> - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
>> + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
>> + <&mdss_dsi0_phy 0>,
>> + <&mdss_dsi0_phy 1>,
>
> #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>Got it, will add the h file and change as below in next patch
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,>
> Konrad
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