linux-kernel - Re: [PATCH v1] ufs: ufs-qcom: Align programming sequence of Shared ICE for UFS controller v5

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <mhridnexscaevsmssu6k3l4x276cj63gl2rlvypym23kj2kgov@pw323zkhqcrg>
Date: Wed, 6 Aug 2025 23:09:00 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Palash Kambar <quic_pkambar@...cinc.com>, 
	James.Bottomley@...senpartnership.com, martin.petersen@...cle.com, linux-arm-msm@...r.kernel.org, 
	linux-scsi@...r.kernel.org, linux-kernel@...r.kernel.org, quic_nitirawa@...cinc.com
Subject: Re: [PATCH v1] ufs: ufs-qcom: Align programming sequence of Shared
 ICE for UFS controller v5

On Wed, Aug 06, 2025 at 02:56:43PM GMT, Konrad Dybcio wrote:
> On 8/6/25 1:14 PM, Manivannan Sadhasivam wrote:
> > On Wed, Aug 06, 2025 at 12:04:09PM GMT, Palash Kambar wrote:
> >> Disable of AES core in Shared ICE is not supported during power
> >> collapse for UFS Host Controller V5.0.
> >>
> >> Hence follow below steps to reset the ICE upon exiting power collapse
> >> and align with Hw programming guide.
> >>
> >> a. Write 0x18 to UFS_MEM_ICE_CFG
> >> b. Write 0x0 to UFS_MEM_ICE_CFG
> >>
> >> Signed-off-by: Palash Kambar <quic_pkambar@...cinc.com>
> >> ---
> 
> [...]
> 
> > 
> >> +		ufshcd_readl(hba, UFS_MEM_ICE);
> >> +		ufshcd_writel(hba, 0x0, UFS_MEM_ICE);
> >> +		ufshcd_readl(hba, UFS_MEM_ICE);
> > 
> > Why do you need readl()? Writes to device memory won't get reordered.
> 
> I'm not sure if we need a delay between them, otherwise they'll happen
> within a couple cycles of each other which may not be enough since this
> is a synchronous reset and the clock period is 20-50ns when running at
> XO (19.2 / 38.4 MHz) rate
> 

IIUC, the second register write is just reenabling the mask, so there is no
delay required between these two writes. If that's not true, and if there is a
delay required, then do:

	ufshcd_writel(0x18);
	ufshcd_readl();
	usleep()/msleep();
	ufshcd_write(0x0);

- Mani

-- 
மணிவண்ணன் சதாசிவம்