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Message-Id: <20250806065514.3688485-5-sw617.shin@samsung.com>
Date: Wed, 6 Aug 2025 15:55:13 +0900
From: Sangwook Shin <sw617.shin@...sung.com>
To: krzk@...nel.org, alim.akhtar@...sung.com, wim@...ux-watchdog.org,
linux@...ck-us.net, semen.protsenko@...aro.org, dongil01.park@...sung.com,
khwan.seo@...sung.com
Cc: linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
linux-watchdog@...r.kernel.org, linux-kernel@...r.kernel.org, Sangwook Shin
<sw617.shin@...sung.com>
Subject: [PATCH v5 4/5] watchdog: s3c2410_wdt: exynosautov920: Enable
QUIRK_HAS_32BIT_CNT
Enable QUIRK_HAS_32BIT_CNT to ExynosAutov920 SoC which has 32-bit WTCNT.
Signed-off-by: Sangwook Shin <sw617.shin@...sung.com>
---
drivers/watchdog/s3c2410_wdt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 673ab6768688..541870b4d01a 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -357,7 +357,7 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
.cnt_en_bit = 8,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
- QUIRK_HAS_DBGACK_BIT,
+ QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT,
};
static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
@@ -370,7 +370,7 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
.cnt_en_bit = 8,
.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
- QUIRK_HAS_DBGACK_BIT,
+ QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_32BIT_CNT,
};
static const struct of_device_id s3c2410_wdt_match[] = {
--
2.25.1
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