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Message-ID: <CAAhV-H6fDjVFX_gyT3m39j09RWFu4O89FVdEumyV-dzUnU9Wig@mail.gmail.com> Date: Wed, 6 Aug 2025 16:36:50 +0800 From: Huacai Chen <chenhuacai@...nel.org> To: Yao Zi <ziyao@...root.org> Cc: Yinbo Zhu <zhuyinbo@...ngson.cn>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, WANG Xuerui <kernel@...0n.name>, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, loongarch@...ts.linux.dev, Mingcong Bai <jeffbai@...c.io>, Kexy Biscuit <kexybiscuit@...c.io> Subject: Re: [PATCH v3 1/8] dt-bindings: clock: loongson2: Add Loongson 2K0300 compatible On Tue, Aug 5, 2025 at 11:03 PM Yao Zi <ziyao@...root.org> wrote: > > Document the clock controller shipped in Loongson 2K0300 SoC, which > generates various clock signals for SoC peripherals. > > Differing from previous generations of SoCs, 2K0300 requires a 120MHz > external clock input, and a separate dt-binding header is used for > cleanness. > > Signed-off-by: Yao Zi <ziyao@...root.org> > --- > .../bindings/clock/loongson,ls2k-clk.yaml | 21 ++++++-- > MAINTAINERS | 1 + > .../dt-bindings/clock/loongson,ls2k0300-clk.h | 54 +++++++++++++++++++ > 3 files changed, 72 insertions(+), 4 deletions(-) > create mode 100644 include/dt-bindings/clock/loongson,ls2k0300-clk.h > > diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml > index 4f79cdb417ab..47eb6c0f85bc 100644 > --- a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml > +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml > @@ -16,6 +16,7 @@ description: | > properties: > compatible: > enum: > + - loongson,ls2k0300-clk > - loongson,ls2k0500-clk > - loongson,ls2k-clk # This is for Loongson-2K1000 > - loongson,ls2k2000-clk > @@ -24,8 +25,7 @@ properties: > maxItems: 1 > > clocks: > - items: > - - description: 100m ref > + maxItems: 1 > > clock-names: > items: > @@ -36,13 +36,26 @@ properties: > description: > The clock consumer should specify the desired clock by having the clock > ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h > - for the full list of Loongson-2 SoC clock IDs. > + and include/dt-bindings/clock/loongson,ls2k0300-clk.h for the full list of > + Loongson-2 SoC clock IDs. > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: loongson,ls2k0300-clk > + then: > + properties: > + clock-names: false > + else: > + required: > + - clock-names > > required: > - compatible > - reg > - clocks > - - clock-names > - '#clock-cells' > > additionalProperties: false > diff --git a/MAINTAINERS b/MAINTAINERS > index 4912b8a83bbb..7960e65d7dfc 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -14365,6 +14365,7 @@ S: Maintained > F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml > F: drivers/clk/clk-loongson2.c > F: include/dt-bindings/clock/loongson,ls2k-clk.h > +F: include/dt-bindings/clock/loongson,ls2k0300-clk.h I think ls2k0300-clk.h can be merged into ls2k-clk.h Huacai > > LOONGSON SPI DRIVER > M: Yinbo Zhu <zhuyinbo@...ngson.cn> > diff --git a/include/dt-bindings/clock/loongson,ls2k0300-clk.h b/include/dt-bindings/clock/loongson,ls2k0300-clk.h > new file mode 100644 > index 000000000000..5e8f7b2f33f2 > --- /dev/null > +++ b/include/dt-bindings/clock/loongson,ls2k0300-clk.h > @@ -0,0 +1,54 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ > +/* > + * Copyright (C) 2025 Yao Zi <ziyao@...root.org> > + */ > +#ifndef _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > +#define _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > + > +/* Derivied from REFCLK */ > +#define LS2K0300_CLK_STABLE 0 > +#define LS2K0300_PLL_NODE 1 > +#define LS2K0300_PLL_DDR 2 > +#define LS2K0300_PLL_PIX 3 > +#define LS2K0300_CLK_THSENS 4 > + > +/* Derived from PLL_NODE */ > +#define LS2K0300_CLK_NODE_DIV 5 > +#define LS2K0300_CLK_NODE_PLL_GATE 6 > +#define LS2K0300_CLK_NODE_SCALE 7 > +#define LS2K0300_CLK_NODE_GATE 8 > +#define LS2K0300_CLK_GMAC_DIV 9 > +#define LS2K0300_CLK_GMAC_GATE 10 > +#define LS2K0300_CLK_I2S_DIV 11 > +#define LS2K0300_CLK_I2S_SCALE 12 > +#define LS2K0300_CLK_I2S_GATE 13 > + > +/* Derived from PLL_DDR */ > +#define LS2K0300_CLK_DDR_DIV 14 > +#define LS2K0300_CLK_DDR_GATE 15 > +#define LS2K0300_CLK_NET_DIV 16 > +#define LS2K0300_CLK_NET_GATE 17 > +#define LS2K0300_CLK_DEV_DIV 18 > +#define LS2K0300_CLK_DEV_GATE 19 > + > +/* Derived from PLL_PIX */ > +#define LS2K0300_CLK_PIX_DIV 20 > +#define LS2K0300_CLK_PIX_PLL_GATE 21 > +#define LS2K0300_CLK_PIX_SCALE 22 > +#define LS2K0300_CLK_PIX_GATE 23 > +#define LS2K0300_CLK_GMACBP_DIV 24 > +#define LS2K0300_CLK_GMACBP_GATE 25 > + > +/* Derived from CLK_DEV */ > +#define LS2K0300_CLK_USB_SCALE 26 > +#define LS2K0300_CLK_USB_GATE 27 > +#define LS2K0300_CLK_APB_SCALE 28 > +#define LS2K0300_CLK_APB_GATE 29 > +#define LS2K0300_CLK_BOOT_SCALE 30 > +#define LS2K0300_CLK_BOOT_GATE 31 > +#define LS2K0300_CLK_SDIO_SCALE 32 > +#define LS2K0300_CLK_SDIO_GATE 33 > + > +#define LS2K0300_CLK_GMAC_IN 34 > + > +#endif // _DT_BINDINGS_CLK_LOONGSON_LS2K300_H_ > -- > 2.50.1 >
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