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Message-ID: <70bd9beb-2f7f-4132-88a4-8d81d70ac50b@kernel.org>
Date: Wed, 6 Aug 2025 13:47:34 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Varadarajan Narayanan <quic_varada@...cinc.com>, andersson@...nel.org,
mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, konradybcio@...nel.org,
rafael@...nel.org, viresh.kumar@...aro.org, ilia.lin@...nel.org,
djakov@...nel.org, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org
Cc: Sricharan Ramabadhran <quic_srichara@...cinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Md Sadre Alam <quic_mdalam@...cinc.com>
Subject: Re: [PATCH v6 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424
apss clock controller
On 06/08/2025 13:28, Varadarajan Narayanan wrote:
> From: Sricharan Ramabadhran <quic_srichara@...cinc.com>
>
> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> The RCG and PLL have a separate register space from the GCC.
> Also the L3 cache has a separate pll and needs to be scaled along
> with the CPU.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
This is oddly placed. Did you use b4 that it appeared here?
> Co-developed-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> Signed-off-by: Md Sadre Alam <quic_mdalam@...cinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> [ Added interconnect related changes ]
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> ---
> v6: Add 'Reviewed-by: Krzysztof Kozlowski'
> Drop 'clock-names'
Best regards,
Krzysztof
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