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Message-ID: <CAMuHMdXu+sYNO2=QU+9e7E1pMFpgWBPEh_VoWgVPb-5aDG6D_w@mail.gmail.com>
Date: Wed, 6 Aug 2025 14:57:26 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Linus Walleij <linus.walleij@...aro.org>, linux-renesas-soc@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
John Madieu <john.madieu.xa@...renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 5/7] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}
Hi Prabhakar,
On Wed, 9 Jul 2025 at 18:08, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing
> rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a
> pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit
> positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR
> locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded
> PFC_OEN define and obsolete per-SoC OEN helpers.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -270,6 +270,7 @@ struct rzg2l_hwcfg {
> u8 func_base;
> u8 oen_max_pin;
> u8 oen_max_port;
> + bool oen_pwpr_lock;
While u8 and bool do have the same size, please keep the bools grouped
ogether.
> };
>
> struct rzg2l_dedicated_configs {
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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