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Message-ID: <20250807-untrained-anthology-bcf760fe73cb@spud>
Date: Thu, 7 Aug 2025 17:19:51 +0100
From: Conor Dooley <conor@...nel.org>
To: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
Cc: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Yixun Lan <dlan@...too.org>,
	Alex Elder <elder@...cstar.com>, Haylen Chu <heylenay@....org>,
	Inochi Amaoto <inochiama@...look.com>, linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	spacemit@...ts.linux.dev, linux-kernel@...r.kernel.org,
	Jinmei Wei <weijinmei@...ux.spacemit.com>
Subject: Re: [PATCH 1/2] dt-bindings: clock: spacemit: introduce i2s pre-clock

On Thu, Aug 07, 2025 at 09:30:10AM +0800, Troy Mitchell wrote:
> Previously, the K1 clock driver did not include the parent clocks of
> the I2S sysclk.
> 
> This patch adds their definitions to allow proper registration
> in the driver and usage in the device tree.
> 
> Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")

I'm not sure that a fixes tag is suitable here, seems to be some new
feature/development. The driver change seems to talk about how modelling
as a fixed-clock is incorrect, but this change mentions none of that.
Without whatever context that provides, it's hard to see how this can be
justified as a fix rather than a new feature being added.

> Signed-off-by: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
> ---
>  include/dt-bindings/clock/spacemit,k1-syscon.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
> index 2714c3fe66cd5b49e12c8b20689f5b01da36b774..524268246fedd3f1238320f35244baf32354fbd2 100644
> --- a/include/dt-bindings/clock/spacemit,k1-syscon.h
> +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
> @@ -77,6 +77,9 @@
>  #define CLK_I2S_BCLK		30
>  #define CLK_APB			31
>  #define CLK_WDT_BUS		32
> +#define CLK_I2S_153P6		33
> +#define CLK_I2S_153P6_BASE	34
> +#define CLK_I2S_SYSCLK_SRC	35
>  
>  /* MPMU resets */
>  #define RESET_WDT		0
> 
> -- 
> 2.50.1
> 
> 

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