linux-kernel - Re: [RESEND PATCH 2/2] PCI: stm32: use pinctrl_pm_select_init_state() in stm32_pcie_resume

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20250807180519.GA56557@bhelgaas>
Date: Thu, 7 Aug 2025 13:05:19 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Christian Bruel <christian.bruel@...s.st.com>
Cc: lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
	robh@...nel.org, bhelgaas@...gle.com, mcoquelin.stm32@...il.com,
	alexandre.torgue@...s.st.com, linus.walleij@...aro.org,
	linux-pci@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	linux-gpio@...r.kernel.org, kernel test robot <lkp@...el.com>
Subject: Re: [RESEND PATCH 2/2] PCI: stm32: use
 pinctrl_pm_select_init_state() in stm32_pcie_resume_noirq()

On Thu, Jul 17, 2025 at 08:30:42AM +0200, Christian Bruel wrote:
> Replace direct access to dev->pins->init_state with the new helper
> pinctrl_pm_select_init_state() to select the init pinctrl state.
> This fixes build issues when CONFIG_PINCTRL is not defined.
> 
> Signed-off-by: Christian Bruel <christian.bruel@...s.st.com>
> Reported-by: Bjorn Helgaas <bhelgaas@...gle.com>  
> Reported-by: kernel test robot <lkp@...el.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202506260920.bmQ9hQ9s-lkp@intel.com/
> Fixes: 633f42f48af5 ("PCI: stm32: Add PCIe host support for STM32MP25")

633f42f48af5 is still on pci/controller/dwc-stm32, but only for
reference.  After v6.17-rc1, we will need to rebase to it and figure
out the merge strategy.

Part of that will be to restructure 633f42f48af5 and the material
below such that there is no build issue at any point in the series.

> ---
>  drivers/pci/controller/dwc/pcie-stm32.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-stm32.c b/drivers/pci/controller/dwc/pcie-stm32.c
> index 50fae5f5ced2..c1d803dc3778 100644
> --- a/drivers/pci/controller/dwc/pcie-stm32.c
> +++ b/drivers/pci/controller/dwc/pcie-stm32.c
> @@ -28,6 +28,7 @@ struct stm32_pcie {
>  	struct clk *clk;
>  	struct gpio_desc *perst_gpio;
>  	struct gpio_desc *wake_gpio;
> +	bool   have_pinctrl_init;
>  };
>  
>  static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie)
> @@ -91,10 +92,10 @@ static int stm32_pcie_resume_noirq(struct device *dev)
>  	/*
>  	 * The core clock is gated with CLKREQ# from the COMBOPHY REFCLK,
>  	 * thus if no device is present, must force it low with an init pinmux
> -	 * to be able to access the DBI registers.
> +	 * if present to be able to access the DBI registers.
>  	 */
> -	if (!IS_ERR(dev->pins->init_state))
> -		ret = pinctrl_select_state(dev->pins->p, dev->pins->init_state);
> +	if (stm32_pcie->have_pinctrl_init)
> +		ret = pinctrl_pm_select_init_state(dev);
>  	else
>  		ret = pinctrl_pm_select_default_state(dev);
>  
> @@ -274,6 +275,9 @@ static int stm32_pcie_probe(struct platform_device *pdev)
>  		return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst),
>  				     "Failed to get PCIe reset\n");
>  
> +	if (device_property_match_string(dev, "pinctrl-names", PINCTRL_STATE_INIT) >= 0)
> +		stm32_pcie->have_pinctrl_init = true;
> +
>  	ret = stm32_pcie_parse_port(stm32_pcie);
>  	if (ret)
>  		return ret;
> -- 
> 2.34.1
>