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Message-ID: <87fre2pd9d.fsf@yellow.woof>
Date: Fri, 08 Aug 2025 07:56:46 +0200
From: Nam Cao <namcao@...utronix.de>
To: Thomas Gleixner <tglx@...utronix.de>, Inochi Amaoto
<inochiama@...il.com>, Chen Wang <unicorn_wang@...look.com>
Cc: Inochi Amaoto <inochiama@...il.com>, linux-kernel@...r.kernel.org, Anup
Patel <anup@...infault.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Samuel Holland <samuel.holland@...ive.com>, Marc Zyngier <maz@...nel.org>
Subject: Re: Affinity setting problem for emulated MSI on PLIC
Thomas Gleixner <tglx@...utronix.de> writes:
> Cc'ing more people as this goes way beyond the SG204x driver
Sorry, I missed this email..
> @@ -179,12 +181,57 @@ static int plic_set_affinity(struct irq_
> if (cpu >= nr_cpu_ids)
> return -EINVAL;
>
> - plic_irq_disable(d);
> + /* Invalidate the original routing entry */
> + plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0);
>
> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>
> - if (!irqd_irq_disabled(d))
> - plic_irq_enable(d);
> + /*
> + * Update the routing entry for the new target CPU.
> + *
> + * The below comment is not for a final patch, it's just
> + * documentation for this combo patch, which obviously needs to be
> + * split up into a gazillion of patches. So I use this as a notepad
> + * in order to not forget the gory details, which are changelog
> + * material :)
> + *
> + * This is on purpose not bug compatible with the current
> + * implementation, which unmasked the interrupt unconditionally due
> + * to:
> + *
> + * if (!irqd_irq_disabled(d))
> + * plic_irq_enable(d);
> + *
> + * which is broken as it unconditionally unmasks a masked
> + * interrupt. This was introduced with commit
> + *
> + * 6b1e0651e9ce ("irqchip/sifive-plic: Unmask interrupt in plic_irq_enable()")
Right, my bad.
> + *
> + * which in turn tried to fix the problem, which was introduced by
> + * commit
> + *
> + * a1706a1c5062 ("irqchip/sifive-plic: Separate the enable and mask operations")
> + *
> + * 6b1e0651e9ce is probably harmless, but I'm too tired and can't
> + * be bothered to validate it. See below.
> + *
> + * This all needs real scrutiny and has to be validated against
> + * both specification and implementations.
> + *
> + * AFAICT, toggling unconditionally is the right thing to do, but I
> + * might be completely wrong as ususal.
Is it not possible that affinity is setup while the interrupt is
disabled? Because in that case, toggling unconditionally would enable a
disabled interrupt.
> For me the two mentioned
> + * commits above seem to be contradictionary, but my tired brain
> + * can't decode it right now and therefore I leave that for the
> + * PLIC wizards as _their_ homework.
Not sure if I am included in the "PLIC wizards". But they are not contradictionary:
a1706a1c5062 ("irqchip/sifive-plic: Separate the enable and mask operations")
Before this commit, the enable bits and the priority bits are both
changed in irq_mask(). There was no irq_enable().
This commit separates them, irq_mask() sets priority bits while
irq_enable() sets the enable bits.
6b1e0651e9ce ("irqchip/sifive-plic: Unmask interrupt in plic_irq_enable()")
This commit changed irq_enable() to also set the priority bits.
> Not that I have high
> + * expectations on that given the trail of Tested-by and other
> + * tags. "Works for me" by some definition of "works" seems to be
> + * the prevailing principle here. "Correctness first" is obviously
> + * overrated as usual up to the point where the real great hacks
> + * come along to "fix" the resulting sh*t. Unfortunately that costs
> + * the time of people, who have not been responsible for the
> + * problems in the first place...
> + */
> + plic_irq_toggle(cpumask_of(cpu), d, 1);
>
> return IRQ_SET_MASK_OK_DONE;
> }
I could do a staring, see if there are still lurking problems
Nam
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