linux-kernel - Re: [PATCH v1 2/2] pwm: Add the S32G support in the Freescale FTM driver

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Message-ID: <p5pwwdlrldqdkpqtfvgo3dz2liz46ywy7crjfe4nybxmrhlh55@b6v7lccczczs>
Date: Mon, 11 Aug 2025 07:18:47 +0200
From: Uwe Kleine-König <ukleinek@...nel.org>
To: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	Frank.Li@....com, linux-pwm@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Ghennadi.Procopciuc@....com, s32@....com
Subject: Re: [PATCH v1 2/2] pwm: Add the S32G support in the Freescale FTM
 driver

Hello,

On Sun, Aug 10, 2025 at 08:52:18PM +0200, Daniel Lezcano wrote:
> From: Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>
> 
> The Automotive S32G2 and S32G3 platforms include two FTM timers for
> pwm. Each FTM has 6 PWM channels.
> 
> The current Freescale FTM driver supports the iMX8 and the Vybrid
> Family FTM IP. The FTM IP found on the S32G platforms is almost
> identical except for the number of channels and the register mapping.
> 
> These changes allow to deal with different number of channels and
> support the holes found in the register memory mapping for s32gx for
> suspend / resume.
> 
> Tested on a s32g274-rdb2 J5 PWM pin output with signal visualization
> on oscilloscope.
> 
> Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>
> Co-developed-by: Daniel Lezcano <daniel.lezcano@...aro.org>
> Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
> ---
>  drivers/pwm/pwm-fsl-ftm.c | 42 +++++++++++++++++++++++++++++++++++++--
>  1 file changed, 40 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
> index c45a5fca4cbb..cdf2e3572c90 100644
> --- a/drivers/pwm/pwm-fsl-ftm.c
> +++ b/drivers/pwm/pwm-fsl-ftm.c
> @@ -3,6 +3,7 @@
>   *  Freescale FlexTimer Module (FTM) PWM Driver
>   *
>   *  Copyright 2012-2013 Freescale Semiconductor, Inc.
> + *  Copyright 2020-2025 NXP
>   */
>  
>  #include <linux/clk.h>
> @@ -31,6 +32,9 @@ enum fsl_pwm_clk {
>  
>  struct fsl_ftm_soc {
>  	bool has_enable_bits;
> +	bool has_fltctrl;
> +	bool has_fltpol;

All variants (up to now) have .has_fltctrl == .has_fltpol. Is there a
good reason that justifies two bools for the register description?

Also I wonder about the fuss given that the two registers are not used
in the PWM driver. So this is only to prevent reading these registers
via regmap debug stuff? What happens if the memory locations are read
where the other implementations have these registers?

> +	unsigned int npwm;
>  };

Best regards
Uwe

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