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Message-Id: <20250811061104.10326-2-fangyu.yu@linux.alibaba.com>
Date: Mon, 11 Aug 2025 14:10:59 +0800
From: fangyu.yu@...ux.alibaba.com
To: anup@...infault.org,
	paul.walmsley@...ive.com,
	palmer@...belt.com,
	aou@...s.berkeley.edu,
	alex@...ti.fr,
	atishp@...shpatra.org,
	tjeznach@...osinc.com,
	joro@...tes.org,
	will@...nel.org,
	robin.murphy@....com,
	sunilvl@...tanamicro.com,
	rafael.j.wysocki@...el.com,
	tglx@...utronix.de,
	ajones@...tanamicro.com
Cc: guoren@...ux.alibaba.com,
	guoren@...nel.org,
	kvm@...r.kernel.org,
	kvm-riscv@...ts.infradead.org,
	linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	iommu@...ts.linux.dev,
	Fangyu Yu <fangyu.yu@...ux.alibaba.com>
Subject: [RFC PATCH 1/6] RISC-V: Add more elements to irqbypass vcpu_info

From: Fangyu Yu <fangyu.yu@...ux.alibaba.com>

To support MRIF mode, we need to add more elements to
let the iommu driver get the ppn of MRIF.

Signed-off-by: Fangyu Yu <fangyu.yu@...ux.alibaba.com>
---
 arch/riscv/include/asm/irq.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index 8588667cbb5f..6293ac00e051 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -30,6 +30,9 @@ struct riscv_iommu_vcpu_info {
 	u32 group_index_shift;
 	u64 gpa;
 	u64 hpa;
+	u32 host_irq;
+	bool mrif;
+	struct msi_msg *host_msg;
 };
 
 #ifdef CONFIG_ACPI
-- 
2.49.0


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